126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/*
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* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_device_registers.h"
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#include "fsl_lpspi.h"
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#include "fsl_debug_console.h"
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#include "pin_mux.h"
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#include "board.h"
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#include "fsl_common.h"
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#if ((defined FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT))
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#include "fsl_intmux.h"
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#endif
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define LPSPI_TRANSFER_SIZE 64U /*! Transfer dataSize */
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#define LPSPI_TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */
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#define BOARD_EEPROM_LPSPI_BASEADDR (LPSPI1)
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#define BOARD_LPSPI_IRQN LPSPI1_IRQn
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#define BOARD_LPSPI_IRQHandler LPSPI1_IRQHandler
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#define BOARD_LPSPI_PCS_FOR_INIT (kLPSPI_Pcs0)
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#define BOARD_LPSPI_PCS_FOR_TRANSFER (kLPSPI_MasterPcs0)
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/* Select USB1 PLL PFD0 (392.72 MHz) as lpspi clock source */
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#define BOARD_LPSPI_CLOCK_SOURCE_SELECT (1U)
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/* Clock divider for master lpspi clock source */
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#define BOARD_LPSPI_CLOCK_SOURCE_DIVIDER (7U)
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#define BOARD_LPSPI_CLK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (BOARD_LPSPI_CLOCK_SOURCE_DIVIDER + 1U))
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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static void LPSPI_Init(void)
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{
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lpspi_master_config_t masterConfig;
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/* Master config */
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LPSPI_MasterGetDefaultConfig(&masterConfig);
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masterConfig.baudRate = 500000U;
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masterConfig.bitsPerFrame = 8;
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masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
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masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
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masterConfig.direction = kLPSPI_MsbFirst;
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masterConfig.whichPcs = BOARD_LPSPI_PCS_FOR_INIT;
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masterConfig.pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
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masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
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masterConfig.dataOutConfig = kLpspiDataOutTristate;
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masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;
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masterConfig.enableInputDelay = false;
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LPSPI_MasterInit(BOARD_EEPROM_LPSPI_BASEADDR, &masterConfig, BOARD_LPSPI_CLK_FREQ);
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}
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/*!
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* @brief Main function
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*/
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int main(void)
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{
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uint8_t i;
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lpspi_transfer_t masterXfer;
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uint8_t masterRxData[LPSPI_TRANSFER_SIZE] = {0};
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uint8_t masterTxData[LPSPI_TRANSFER_SIZE] = {0};
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/* Init board hardware. */
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BOARD_ConfigMPU();
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BOARD_InitBootPins();
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BOARD_InitBootClocks();
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BOARD_InitDebugConsole();
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/*Set clock source for LPSPI*/
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CLOCK_SetMux(kCLOCK_LpspiMux, BOARD_LPSPI_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_LpspiDiv, BOARD_LPSPI_CLOCK_SOURCE_DIVIDER);
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PRINTF("\r\n***LPSPI Loopback Demo***\r\n");
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LPSPI_Init();
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for (i = 0; i < LPSPI_TRANSFER_SIZE; i++)
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{
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masterTxData[i] = i;
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}
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/*Start master transfer*/
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masterXfer.txData = masterTxData;
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masterXfer.rxData = masterRxData;
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masterXfer.dataSize = LPSPI_TRANSFER_SIZE;
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masterXfer.configFlags = BOARD_LPSPI_PCS_FOR_TRANSFER | kLPSPI_MasterPcsContinuous;
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LPSPI_MasterTransferBlocking(BOARD_EEPROM_LPSPI_BASEADDR, &masterXfer);
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/* Compare Tx and Rx data. */
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for (i = 0; i < LPSPI_TRANSFER_SIZE; i++)
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{
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if (masterTxData[i] != masterRxData[i])
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{
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break;
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}
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}
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if (LPSPI_TRANSFER_SIZE == i)
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{
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PRINTF("LPSPI loopback test pass!!!");
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}
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else
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{
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PRINTF("LPSPI loopback test fail!!!");
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}
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while (1)
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{
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__NOP();
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}
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}
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