409 lines
14 KiB
C
409 lines
14 KiB
C
/*
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* Copyright 2020-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_phyksz8081.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the PHY KSZ8081 vendor defined registers. */
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#define PHY_INTR_CONTROL_STATUS_REG (0x1BU) /*!< The PHY interrupt control/status register. */
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#define PHY_CONTROL1_REG (0x1EU) /*!< The PHY control one register. */
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#define PHY_CONTROL2_REG (0x1FU) /*!< The PHY control two register. */
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/*! @brief Defines the PHY KSZ8081 ID number. */
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#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1 */
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/*! @brief Defines the mask flag of operation mode in interrupt control/status registers */
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#define PHY_INTR_CONTROL_STATUS_LINK_UP_MASK ((uint16_t)0x0100U) /*!< The PHY link up interrupt mask. */
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#define PHY_INTR_CONTROL_STATUS_LINK_DOWN_MASK ((uint16_t)0x0400U) /*!< The PHY link down interrupt mask. */
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/*! @brief Defines the mask flag of operation mode in control registers */
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#define PHY_CTL2_REMOTELOOP_MASK ((uint16_t)0x0004U) /*!< The PHY remote loopback mask. */
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#define PHY_CTL2_REFCLK_SELECT_MASK ((uint16_t)0x0080U) /*!< The PHY RMII reference clock select. */
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#define PHY_CTL2_INTR_LEVEL_MASK ((uint16_t)0x0200U) /*!< The PHY interrupt level mask. */
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#define PHY_CTL1_10HALFDUPLEX_MASK ((uint16_t)0x0001U) /*!< The PHY 10M half duplex mask. */
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#define PHY_CTL1_100HALFDUPLEX_MASK ((uint16_t)0x0002U) /*!< The PHY 100M half duplex mask. */
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#define PHY_CTL1_10FULLDUPLEX_MASK ((uint16_t)0x0005U) /*!< The PHY 10M full duplex mask. */
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#define PHY_CTL1_100FULLDUPLEX_MASK ((uint16_t)0x0006U) /*!< The PHY 100M full duplex mask. */
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#define PHY_CTL1_SPEEDUPLX_MASK ((uint16_t)0x0007U) /*!< The PHY speed and duplex mask. */
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#define PHY_CTL1_ENERGYDETECT_MASK ((uint16_t)0x0010U) /*!< The PHY signal present on rx differential pair. */
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#define PHY_CTL1_LINKUP_MASK ((uint16_t)0x0100U) /*!< The PHY link up. */
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#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
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/*! @brief Defines the timeout macro. */
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#define PHY_READID_TIMEOUT_COUNT (1000U)
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/*! @brief Defines the PHY resource interface. */
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#define PHY_KSZ8081_WRITE(handle, regAddr, data) \
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(((phy_ksz8081_resource_t *)(handle)->resource)->write((handle)->phyAddr, regAddr, data))
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#define PHY_KSZ8081_READ(handle, regAddr, pData) \
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(((phy_ksz8081_resource_t *)(handle)->resource)->read((handle)->phyAddr, regAddr, pData))
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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const phy_operations_t phyksz8081_ops = {.phyInit = PHY_KSZ8081_Init,
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.phyWrite = PHY_KSZ8081_Write,
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.phyRead = PHY_KSZ8081_Read,
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.getAutoNegoStatus = PHY_KSZ8081_GetAutoNegotiationStatus,
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.getLinkStatus = PHY_KSZ8081_GetLinkStatus,
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.getLinkSpeedDuplex = PHY_KSZ8081_GetLinkSpeedDuplex,
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.setLinkSpeedDuplex = PHY_KSZ8081_SetLinkSpeedDuplex,
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.enableLoopback = PHY_KSZ8081_EnableLoopback,
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.enableLinkInterrupt = PHY_KSZ8081_EnableLinkInterrupt,
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.clearInterrupt = PHY_KSZ8081_ClearInterrupt};
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t PHY_KSZ8081_Init(phy_handle_t *handle, const phy_config_t *config)
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{
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uint32_t counter = PHY_READID_TIMEOUT_COUNT;
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status_t result = kStatus_Success;
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uint16_t regValue = 0;
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/* Assign PHY address and operation resource. */
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handle->phyAddr = config->phyAddr;
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handle->resource = config->resource;
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/* Check PHY ID. */
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do
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{
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result = PHY_KSZ8081_READ(handle, PHY_ID1_REG, ®Value);
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if (result != kStatus_Success)
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{
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return result;
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}
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counter--;
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} while ((regValue != PHY_CONTROL_ID1) && (counter != 0U));
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if (counter == 0U)
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{
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return kStatus_Fail;
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}
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/* Reset PHY. */
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result = PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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if (result == kStatus_Success)
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{
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#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
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result = PHY_KSZ8081_READ(handle, PHY_CONTROL2_REG, ®Value);
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if (result != kStatus_Success)
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{
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return result;
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}
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result = PHY_KSZ8081_WRITE(handle, PHY_CONTROL2_REG, (regValue | PHY_CTL2_REFCLK_SELECT_MASK));
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if (result != kStatus_Success)
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{
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return result;
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}
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#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
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if (config->autoNeg)
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{
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/* Set the auto-negotiation then start it. */
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result = PHY_KSZ8081_WRITE(
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handle, PHY_AUTONEG_ADVERTISE_REG,
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(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK |
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PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK));
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if (result == kStatus_Success)
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{
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result = PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG,
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(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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else
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{
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/* This PHY only supports 10/100M speed. */
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assert(config->speed <= kPHY_Speed100M);
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/* Disable isolate mode */
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result = PHY_KSZ8081_READ(handle, PHY_BASICCONTROL_REG, ®Value);
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if (result != kStatus_Success)
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{
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return result;
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}
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regValue &= ~PHY_BCTL_ISOLATE_MASK;
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result = PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, regValue);
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if (result != kStatus_Success)
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{
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return result;
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}
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/* Disable the auto-negotiation and set user-defined speed/duplex configuration. */
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result = PHY_KSZ8081_SetLinkSpeedDuplex(handle, config->speed, config->duplex);
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}
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if (result != kStatus_Success)
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{
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return result;
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}
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/* Set PHY link status management interrupt. */
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result = PHY_KSZ8081_EnableLinkInterrupt(handle, config->intrType);
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}
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return result;
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}
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status_t PHY_KSZ8081_Write(phy_handle_t *handle, uint8_t phyReg, uint16_t data)
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{
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return PHY_KSZ8081_WRITE(handle, phyReg, data);
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}
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status_t PHY_KSZ8081_Read(phy_handle_t *handle, uint8_t phyReg, uint16_t *pData)
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{
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return PHY_KSZ8081_READ(handle, phyReg, pData);
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}
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status_t PHY_KSZ8081_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status)
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{
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assert(status);
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status_t result;
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uint16_t regValue;
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*status = false;
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/* Check auto negotiation complete. */
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result = PHY_KSZ8081_READ(handle, PHY_BASICSTATUS_REG, ®Value);
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if (result == kStatus_Success)
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{
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if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U)
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{
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*status = true;
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}
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}
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return result;
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}
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status_t PHY_KSZ8081_GetLinkStatus(phy_handle_t *handle, bool *status)
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{
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assert(status);
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status_t result;
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uint16_t regValue;
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/* Read the basic status register. */
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result = PHY_KSZ8081_READ(handle, PHY_BASICSTATUS_REG, ®Value);
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if (result == kStatus_Success)
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{
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if ((PHY_BSTATUS_LINKSTATUS_MASK & regValue) != 0U)
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{
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/* Link up. */
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*status = true;
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}
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else
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{
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/* Link down. */
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*status = false;
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}
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}
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return result;
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}
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status_t PHY_KSZ8081_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex)
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{
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assert(!((speed == NULL) && (duplex == NULL)));
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status_t result;
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uint16_t regValue;
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uint16_t flag;
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/* Read the control register. */
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result = PHY_KSZ8081_READ(handle, PHY_CONTROL1_REG, ®Value);
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if (result == kStatus_Success)
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{
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if (speed != NULL)
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{
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flag = regValue & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_100HALFDUPLEX_MASK == flag) || (PHY_CTL1_100FULLDUPLEX_MASK == flag))
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{
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*speed = kPHY_Speed100M;
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}
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else
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{
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*speed = kPHY_Speed10M;
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}
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}
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if (duplex != NULL)
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{
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flag = regValue & PHY_CTL1_SPEEDUPLX_MASK;
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if ((PHY_CTL1_10FULLDUPLEX_MASK == flag) || (PHY_CTL1_100FULLDUPLEX_MASK == flag))
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{
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*duplex = kPHY_FullDuplex;
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}
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else
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{
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*duplex = kPHY_HalfDuplex;
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}
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}
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}
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return result;
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}
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status_t PHY_KSZ8081_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex)
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{
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/* This PHY only supports 10/100M speed. */
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assert(speed <= kPHY_Speed100M);
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status_t result;
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uint16_t regValue;
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result = PHY_KSZ8081_READ(handle, PHY_BASICCONTROL_REG, ®Value);
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if (result == kStatus_Success)
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{
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/* Disable the auto-negotiation and set according to user-defined configuration. */
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regValue &= ~PHY_BCTL_AUTONEG_MASK;
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if (speed == kPHY_Speed100M)
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{
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regValue |= PHY_BCTL_SPEED0_MASK;
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}
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else
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{
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regValue &= ~PHY_BCTL_SPEED0_MASK;
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}
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if (duplex == kPHY_FullDuplex)
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{
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regValue |= PHY_BCTL_DUPLEX_MASK;
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}
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else
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{
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regValue &= ~PHY_BCTL_DUPLEX_MASK;
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}
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result = PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, regValue);
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}
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return result;
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}
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status_t PHY_KSZ8081_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable)
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{
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/* This PHY only supports local/remote loopback and 10/100M speed. */
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assert(mode <= kPHY_RemoteLoop);
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assert(speed <= kPHY_Speed100M);
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status_t result;
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uint16_t regValue;
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/* Set the loop mode. */
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if (enable)
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{
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if (mode == kPHY_LocalLoop)
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{
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if (speed == kPHY_Speed100M)
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{
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regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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else
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{
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regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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}
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return PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, regValue);
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}
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else
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{
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/* Remote loopback only supports 100M full-duplex. */
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assert(speed == kPHY_Speed100M);
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regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
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result = PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, regValue);
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if (result != kStatus_Success)
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{
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return result;
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}
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/* Set the remote loopback bit. */
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result = PHY_KSZ8081_READ(handle, PHY_CONTROL2_REG, ®Value);
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if (result == kStatus_Success)
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{
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return PHY_KSZ8081_WRITE(handle, PHY_CONTROL2_REG, (regValue | PHY_CTL2_REMOTELOOP_MASK));
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}
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}
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}
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else
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{
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/* Disable the loop mode. */
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if (mode == kPHY_LocalLoop)
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{
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/* First read the current status in control register. */
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result = PHY_KSZ8081_READ(handle, PHY_BASICCONTROL_REG, ®Value);
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if (result == kStatus_Success)
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{
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regValue &= ~PHY_BCTL_LOOP_MASK;
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return PHY_KSZ8081_WRITE(handle, PHY_BASICCONTROL_REG, (regValue | PHY_BCTL_RESTART_AUTONEG_MASK));
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}
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}
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else
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{
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/* First read the current status in control one register. */
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result = PHY_KSZ8081_READ(handle, PHY_CONTROL2_REG, ®Value);
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if (result == kStatus_Success)
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{
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return PHY_KSZ8081_WRITE(handle, PHY_CONTROL2_REG, regValue & ~PHY_CTL2_REMOTELOOP_MASK);
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}
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}
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}
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return result;
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}
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status_t PHY_KSZ8081_EnableLinkInterrupt(phy_handle_t *handle, phy_interrupt_type_t type)
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{
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status_t result;
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uint16_t regValue;
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/* Read operation will clear pending interrupt before enable interrupt. */
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result = PHY_KSZ8081_READ(handle, PHY_INTR_CONTROL_STATUS_REG, ®Value);
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if (result == kStatus_Success)
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{
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/* Enable/Disable link up+down interrupt. */
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if (type != kPHY_IntrDisable)
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{
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regValue |= (PHY_INTR_CONTROL_STATUS_LINK_UP_MASK | PHY_INTR_CONTROL_STATUS_LINK_DOWN_MASK);
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}
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else
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{
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regValue &= ~(PHY_INTR_CONTROL_STATUS_LINK_UP_MASK | PHY_INTR_CONTROL_STATUS_LINK_DOWN_MASK);
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}
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result = PHY_KSZ8081_WRITE(handle, PHY_INTR_CONTROL_STATUS_REG, regValue);
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}
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if (result != kStatus_Success)
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{
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return result;
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}
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if (type != kPHY_IntrDisable)
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{
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/* Set link interrupt type. */
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result = PHY_KSZ8081_READ(handle, PHY_CONTROL2_REG, ®Value);
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if (result == kStatus_Success)
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{
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if (type == kPHY_IntrActiveLow)
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{
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regValue &= ~PHY_CTL2_INTR_LEVEL_MASK;
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}
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else
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{
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regValue |= PHY_CTL2_INTR_LEVEL_MASK;
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}
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result = PHY_KSZ8081_WRITE(handle, PHY_CONTROL2_REG, regValue);
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}
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}
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return result;
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}
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status_t PHY_KSZ8081_ClearInterrupt(phy_handle_t *handle)
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{
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uint16_t regValue;
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return PHY_KSZ8081_READ(handle, PHY_INTR_CONTROL_STATUS_REG, ®Value);
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}
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