1566 lines
56 KiB
C
1566 lines
56 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2020, 2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexio_spi.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexio_spi"
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#endif
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/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
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enum _flexio_spi_transfer_states
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{
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kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */
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kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */
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};
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Send a piece of data for SPI.
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*
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* This function computes the number of data to be written into D register or Tx FIFO,
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* and write the data into it. At the same time, this function updates the values in
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* master handle structure.
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*
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* @param base pointer to FLEXIO_SPI_Type structure
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* @param handle Pointer to SPI master handle structure.
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*/
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static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
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/*!
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* @brief Receive a piece of data for SPI master.
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*
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* This function computes the number of data to receive from D register or Rx FIFO,
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* and write the data to destination address. At the same time, this function updates
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* the values in master handle structure.
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*
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* @param base pointer to FLEXIO_SPI_Type structure
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* @param handle Pointer to SPI master handle structure.
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*/
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static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Codes
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******************************************************************************/
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static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base)
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{
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return FLEXIO_GetInstance(base->flexioBase);
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}
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static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
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{
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uint32_t tmpData = FLEXIO_SPI_DUMMYDATA;
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if (handle->txData != NULL)
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{
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/* Transmit data and update tx size/buff. */
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if (handle->bytePerFrame == 1U)
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{
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tmpData = (uint32_t) * (handle->txData);
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handle->txData++;
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}
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else if (handle->bytePerFrame == 2U)
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{
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if (handle->direction == kFLEXIO_SPI_MsbFirst)
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{
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tmpData = (uint32_t)(handle->txData[0]) << 8U;
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tmpData += (uint32_t)handle->txData[1];
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}
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else
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{
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tmpData = (uint32_t)(handle->txData[1]) << 8U;
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tmpData += (uint32_t)handle->txData[0];
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}
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handle->txData += 2U;
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}
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else
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{
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if (handle->direction == kFLEXIO_SPI_MsbFirst)
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{
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tmpData = (uint32_t)(handle->txData[0]) << 24U;
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tmpData += (uint32_t)(handle->txData[1]) << 16U;
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tmpData += (uint32_t)(handle->txData[2]) << 8U;
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tmpData += (uint32_t)handle->txData[3];
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}
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else
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{
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tmpData = (uint32_t)(handle->txData[3]) << 24U;
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tmpData += (uint32_t)(handle->txData[2]) << 16U;
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tmpData += (uint32_t)(handle->txData[1]) << 8U;
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tmpData += (uint32_t)handle->txData[0];
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}
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handle->txData += 4U;
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}
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}
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else
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{
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tmpData = FLEXIO_SPI_DUMMYDATA;
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}
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handle->txRemainingBytes -= handle->bytePerFrame;
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FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
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if (0U == handle->txRemainingBytes)
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{
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FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
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}
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}
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static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
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{
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uint32_t tmpData;
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tmpData = FLEXIO_SPI_ReadData(base, handle->direction);
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if (handle->rxData != NULL)
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{
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if (handle->bytePerFrame == 1U)
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{
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*handle->rxData = (uint8_t)tmpData;
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}
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else if (handle->bytePerFrame == 2U)
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{
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if (handle->direction == kFLEXIO_SPI_LsbFirst)
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{
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*handle->rxData = (uint8_t)(tmpData >> 8);
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handle->rxData++;
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*handle->rxData = (uint8_t)tmpData;
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}
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else
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{
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*handle->rxData = (uint8_t)tmpData;
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handle->rxData++;
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*handle->rxData = (uint8_t)(tmpData >> 8);
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}
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}
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else
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{
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if (handle->direction == kFLEXIO_SPI_LsbFirst)
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{
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*handle->rxData = (uint8_t)(tmpData >> 24U);
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handle->rxData++;
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*handle->rxData = (uint8_t)(tmpData >> 16U);
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handle->rxData++;
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*handle->rxData = (uint8_t)(tmpData >> 8U);
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handle->rxData++;
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*handle->rxData = (uint8_t)tmpData;
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}
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else
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{
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*handle->rxData = (uint8_t)tmpData;
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handle->rxData++;
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*handle->rxData = (uint8_t)(tmpData >> 8U);
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handle->rxData++;
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*handle->rxData = (uint8_t)(tmpData >> 16U);
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handle->rxData++;
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*handle->rxData = (uint8_t)(tmpData >> 24U);
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}
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}
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handle->rxData++;
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}
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handle->rxRemainingBytes -= handle->bytePerFrame;
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}
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/*!
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* brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware,
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* and configures the FlexIO SPI with FlexIO SPI master configuration. The
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* configuration structure can be filled by the user, or be set with default values
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* by the FLEXIO_SPI_MasterGetDefaultConfig().
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*
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* note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low.
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* 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
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* is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud
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* rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO
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* SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
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*
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* Example
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code
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FLEXIO_SPI_Type spiDev = {
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.flexioBase = FLEXIO,
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.SDOPinIndex = 0,
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.SDIPinIndex = 1,
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.SCKPinIndex = 2,
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.CSnPinIndex = 3,
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.shifterIndex = {0,1},
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.timerIndex = {0,1}
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};
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flexio_spi_master_config_t config = {
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.enableMaster = true,
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.enableInDoze = false,
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.enableInDebug = true,
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.enableFastAccess = false,
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.baudRate_Bps = 500000,
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.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
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.direction = kFLEXIO_SPI_MsbFirst,
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.dataMode = kFLEXIO_SPI_8BitMode
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};
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FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz);
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endcode
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*
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* param base Pointer to the FLEXIO_SPI_Type structure.
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* param masterConfig Pointer to the flexio_spi_master_config_t structure.
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* param srcClock_Hz FlexIO source clock in Hz.
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*/
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void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz)
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{
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assert(base != NULL);
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assert(masterConfig != NULL);
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flexio_shifter_config_t shifterConfig;
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flexio_timer_config_t timerConfig;
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uint32_t ctrlReg = 0;
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uint16_t timerDiv = 0;
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uint16_t timerCmp = 0;
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/* Clear the shifterConfig & timerConfig struct. */
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(void)memset(&shifterConfig, 0, sizeof(shifterConfig));
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(void)memset(&timerConfig, 0, sizeof(timerConfig));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate flexio clock. */
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CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Configure FLEXIO SPI Master */
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ctrlReg = base->flexioBase->CTRL;
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ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
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ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
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FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
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if (!masterConfig->enableInDoze)
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{
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ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
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}
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base->flexioBase->CTRL = ctrlReg;
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/* Do hardware configuration. */
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/* 1. Configure the shifter 0 for tx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
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shifterConfig.pinSelect = base->SDOPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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}
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else
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
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/* 2. Configure the shifter 1 for rx. */
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shifterConfig.timerSelect = base->timerIndex[0];
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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shifterConfig.pinSelect = base->SDIPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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}
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else
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{
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
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/*3. Configure the timer 0 for SCK. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
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timerConfig.pinSelect = base->SCKPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
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timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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/* Low 8-bits are used to configure baudrate. */
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timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps);
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timerDiv = timerDiv / 2U - 1U;
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/* High 8-bits are used to configure shift clock edges(transfer width). */
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timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U;
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timerCmp |= timerDiv;
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timerConfig.timerCompare = timerCmp;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
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/* 4. Configure the timer 1 for CSn. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
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timerConfig.pinSelect = base->CSnPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
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timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
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timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
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timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
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timerConfig.timerCompare = 0xFFFFU; /* Never compare. */
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
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}
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/*!
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* brief Resets the FlexIO SPI timer and shifter config.
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*
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* param base Pointer to the FLEXIO_SPI_Type.
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*/
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void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base)
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{
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base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
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base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
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base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
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base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
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base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
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base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
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base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
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base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
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}
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/*!
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* brief Gets the default configuration to configure the FlexIO SPI master. The configuration
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* can be used directly by calling the FLEXIO_SPI_MasterConfigure().
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* Example:
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code
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flexio_spi_master_config_t masterConfig;
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FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig);
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endcode
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* param masterConfig Pointer to the flexio_spi_master_config_t structure.
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*/
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void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig)
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{
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assert(masterConfig != NULL);
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/* Initializes the configure structure to zero. */
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(void)memset(masterConfig, 0, sizeof(*masterConfig));
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masterConfig->enableMaster = true;
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masterConfig->enableInDoze = false;
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masterConfig->enableInDebug = true;
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masterConfig->enableFastAccess = false;
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/* Default baud rate 500kbps. */
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masterConfig->baudRate_Bps = 500000U;
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/* Default CPHA = 0. */
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masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
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/* Default bit count at 8. */
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masterConfig->dataMode = kFLEXIO_SPI_8BitMode;
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}
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/*!
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* brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware
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* configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The
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* configuration structure can be filled by the user, or be set with default values
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* by the FLEXIO_SPI_SlaveGetDefaultConfig().
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*
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* note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored.
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* 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low.
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* 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time
|
|
* is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud
|
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* rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO
|
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* SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8.
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* Example
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code
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FLEXIO_SPI_Type spiDev = {
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.flexioBase = FLEXIO,
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.SDOPinIndex = 0,
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.SDIPinIndex = 1,
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.SCKPinIndex = 2,
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.CSnPinIndex = 3,
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.shifterIndex = {0,1},
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.timerIndex = {0}
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};
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flexio_spi_slave_config_t config = {
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.enableSlave = true,
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.enableInDoze = false,
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.enableInDebug = true,
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.enableFastAccess = false,
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.phase = kFLEXIO_SPI_ClockPhaseFirstEdge,
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.direction = kFLEXIO_SPI_MsbFirst,
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.dataMode = kFLEXIO_SPI_8BitMode
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};
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FLEXIO_SPI_SlaveInit(&spiDev, &config);
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endcode
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* param base Pointer to the FLEXIO_SPI_Type structure.
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* param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
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*/
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void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig)
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{
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assert((base != NULL) && (slaveConfig != NULL));
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flexio_shifter_config_t shifterConfig;
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flexio_timer_config_t timerConfig;
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uint32_t ctrlReg = 0;
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/* Clear the shifterConfig & timerConfig struct. */
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(void)memset(&shifterConfig, 0, sizeof(shifterConfig));
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(void)memset(&timerConfig, 0, sizeof(timerConfig));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate flexio clock. */
|
|
CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]);
|
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
|
|
|
/* Configure FLEXIO SPI Slave */
|
|
ctrlReg = base->flexioBase->CTRL;
|
|
ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
|
|
ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) |
|
|
FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave));
|
|
if (!slaveConfig->enableInDoze)
|
|
{
|
|
ctrlReg |= FLEXIO_CTRL_DOZEN_MASK;
|
|
}
|
|
|
|
base->flexioBase->CTRL = ctrlReg;
|
|
|
|
/* Do hardware configuration. */
|
|
/* 1. Configure the shifter 0 for tx. */
|
|
shifterConfig.timerSelect = base->timerIndex[0];
|
|
shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
|
|
shifterConfig.pinSelect = base->SDOPinIndex;
|
|
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
|
|
shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
|
|
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
|
|
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
|
|
if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
|
|
{
|
|
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
|
|
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
|
|
}
|
|
else
|
|
{
|
|
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
|
|
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
|
|
}
|
|
|
|
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
|
|
|
|
/* 2. Configure the shifter 1 for rx. */
|
|
shifterConfig.timerSelect = base->timerIndex[0];
|
|
shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
|
|
shifterConfig.pinSelect = base->SDIPinIndex;
|
|
shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
|
|
shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
|
|
shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
|
|
shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
|
|
shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
|
|
if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
|
|
{
|
|
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
|
|
}
|
|
else
|
|
{
|
|
shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
|
|
}
|
|
|
|
FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
|
|
|
|
/*3. Configure the timer 0 for shift clock. */
|
|
timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex);
|
|
timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
|
|
timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
|
|
timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
|
|
timerConfig.pinSelect = base->SCKPinIndex;
|
|
timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
|
|
timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
|
|
timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
|
|
timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
|
|
timerConfig.timerReset = kFLEXIO_TimerResetNever;
|
|
timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge;
|
|
timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
|
|
if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge)
|
|
{
|
|
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
|
|
timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
|
|
}
|
|
else
|
|
{
|
|
timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge;
|
|
timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
|
|
}
|
|
|
|
timerConfig.timerCompare = (uint32_t)slaveConfig->dataMode * 2U - 1U;
|
|
|
|
FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
|
|
}
|
|
|
|
/*!
|
|
* brief Gates the FlexIO clock.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type.
|
|
*/
|
|
void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base)
|
|
{
|
|
FLEXIO_SPI_MasterDeinit(base);
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the default configuration to configure the FlexIO SPI slave. The configuration
|
|
* can be used directly for calling the FLEXIO_SPI_SlaveConfigure().
|
|
* Example:
|
|
code
|
|
flexio_spi_slave_config_t slaveConfig;
|
|
FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig);
|
|
endcode
|
|
* param slaveConfig Pointer to the flexio_spi_slave_config_t structure.
|
|
*/
|
|
void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig)
|
|
{
|
|
assert(slaveConfig != NULL);
|
|
|
|
/* Initializes the configure structure to zero. */
|
|
(void)memset(slaveConfig, 0, sizeof(*slaveConfig));
|
|
|
|
slaveConfig->enableSlave = true;
|
|
slaveConfig->enableInDoze = false;
|
|
slaveConfig->enableInDebug = true;
|
|
slaveConfig->enableFastAccess = false;
|
|
/* Default CPHA = 0. */
|
|
slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge;
|
|
/* Default bit count at 8. */
|
|
slaveConfig->dataMode = kFLEXIO_SPI_8BitMode;
|
|
}
|
|
|
|
/*!
|
|
* brief Enables the FlexIO SPI interrupt.
|
|
*
|
|
* This function enables the FlexIO SPI interrupt.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param mask interrupt source. The parameter can be any combination of the following values:
|
|
* arg kFLEXIO_SPI_RxFullInterruptEnable
|
|
* arg kFLEXIO_SPI_TxEmptyInterruptEnable
|
|
*/
|
|
void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
|
|
{
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U)
|
|
{
|
|
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
|
|
}
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U)
|
|
{
|
|
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Disables the FlexIO SPI interrupt.
|
|
*
|
|
* This function disables the FlexIO SPI interrupt.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param mask interrupt source The parameter can be any combination of the following values:
|
|
* arg kFLEXIO_SPI_RxFullInterruptEnable
|
|
* arg kFLEXIO_SPI_TxEmptyInterruptEnable
|
|
*/
|
|
void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask)
|
|
{
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U)
|
|
{
|
|
FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]);
|
|
}
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U)
|
|
{
|
|
FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA,
|
|
* which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param mask SPI DMA source.
|
|
* param enable True means enable DMA, false means disable DMA.
|
|
*/
|
|
void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable)
|
|
{
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_TxDmaEnable) != 0U)
|
|
{
|
|
FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable);
|
|
}
|
|
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_RxDmaEnable) != 0U)
|
|
{
|
|
FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable);
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Gets FlexIO SPI status flags.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* return status flag; Use the status flag to AND the following flag mask and get the status.
|
|
* arg kFLEXIO_SPI_TxEmptyFlag
|
|
* arg kFLEXIO_SPI_RxEmptyFlag
|
|
*/
|
|
|
|
uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base)
|
|
{
|
|
uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase);
|
|
uint32_t status = 0;
|
|
|
|
status = ((shifterStatus & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]);
|
|
status |= (((shifterStatus & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U);
|
|
|
|
return status;
|
|
}
|
|
|
|
/*!
|
|
* brief Clears FlexIO SPI status flags.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param mask status flag
|
|
* The parameter can be any combination of the following values:
|
|
* arg kFLEXIO_SPI_TxEmptyFlag
|
|
* arg kFLEXIO_SPI_RxEmptyFlag
|
|
*/
|
|
|
|
void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask)
|
|
{
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U)
|
|
{
|
|
FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]);
|
|
}
|
|
if ((mask & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U)
|
|
{
|
|
FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param baudRate_Bps Baud Rate needed in Hz.
|
|
* param srcClockHz SPI source clock frequency in Hz.
|
|
*/
|
|
void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz)
|
|
{
|
|
uint16_t timerDiv = 0;
|
|
uint16_t timerCmp = 0;
|
|
FLEXIO_Type *flexioBase = base->flexioBase;
|
|
|
|
/* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
|
|
timerDiv = (uint16_t)(srcClockHz / baudRate_Bps);
|
|
timerDiv = timerDiv / 2U - 1U;
|
|
|
|
timerCmp = (uint16_t)(flexioBase->TIMCMP[base->timerIndex[0]]);
|
|
timerCmp &= 0xFF00U;
|
|
timerCmp |= timerDiv;
|
|
|
|
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
|
|
}
|
|
|
|
/*!
|
|
* brief Sends a buffer of data bytes.
|
|
*
|
|
* note This function blocks using the polling method until all bytes have been sent.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param direction Shift direction of MSB first or LSB first.
|
|
* param buffer The data bytes to send.
|
|
* param size The number of data bytes to send.
|
|
* retval kStatus_Success Successfully create the handle.
|
|
* retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
|
|
*/
|
|
status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
|
|
flexio_spi_shift_direction_t direction,
|
|
const uint8_t *buffer,
|
|
size_t size)
|
|
{
|
|
assert(buffer != NULL);
|
|
assert(size != 0U);
|
|
|
|
#if SPI_RETRY_TIMES
|
|
uint32_t waitTimes;
|
|
#endif
|
|
|
|
while (0U != size--)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
#if SPI_RETRY_TIMES
|
|
waitTimes = SPI_RETRY_TIMES;
|
|
while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) &&
|
|
(0U != --waitTimes))
|
|
#else
|
|
while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag))
|
|
#endif
|
|
{
|
|
}
|
|
#if SPI_RETRY_TIMES
|
|
if (waitTimes == 0U)
|
|
{
|
|
return kStatus_FLEXIO_SPI_Timeout;
|
|
}
|
|
#endif
|
|
FLEXIO_SPI_WriteData(base, direction, *buffer++);
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Receives a buffer of bytes.
|
|
*
|
|
* note This function blocks using the polling method until all bytes have been received.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param direction Shift direction of MSB first or LSB first.
|
|
* param buffer The buffer to store the received bytes.
|
|
* param size The number of data bytes to be received.
|
|
* param direction Shift direction of MSB first or LSB first.
|
|
* retval kStatus_Success Successfully create the handle.
|
|
* retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
|
|
*/
|
|
status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base,
|
|
flexio_spi_shift_direction_t direction,
|
|
uint8_t *buffer,
|
|
size_t size)
|
|
{
|
|
assert(buffer != NULL);
|
|
assert(size != 0U);
|
|
|
|
#if SPI_RETRY_TIMES
|
|
uint32_t waitTimes;
|
|
#endif
|
|
|
|
while (0U != size--)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
#if SPI_RETRY_TIMES
|
|
waitTimes = SPI_RETRY_TIMES;
|
|
while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) &&
|
|
(0U != --waitTimes))
|
|
#else
|
|
while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag))
|
|
#endif
|
|
{
|
|
}
|
|
#if SPI_RETRY_TIMES
|
|
if (waitTimes == 0U)
|
|
{
|
|
return kStatus_FLEXIO_SPI_Timeout;
|
|
}
|
|
#endif
|
|
*buffer++ = (uint8_t)FLEXIO_SPI_ReadData(base, direction);
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Receives a buffer of bytes.
|
|
*
|
|
* note This function blocks via polling until all bytes have been received.
|
|
*
|
|
* param base pointer to FLEXIO_SPI_Type structure
|
|
* param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t.
|
|
* retval kStatus_Success Successfully create the handle.
|
|
* retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
|
|
*/
|
|
status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer)
|
|
{
|
|
flexio_spi_shift_direction_t direction;
|
|
uint8_t bytesPerFrame;
|
|
uint32_t dataMode = 0;
|
|
uint16_t timerCmp = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]);
|
|
uint32_t tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
|
|
#if SPI_RETRY_TIMES
|
|
uint32_t waitTimes;
|
|
#endif
|
|
|
|
timerCmp &= 0x00FFU;
|
|
|
|
if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
|
|
{
|
|
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
|
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
|
|
FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
|
|
}
|
|
else
|
|
{
|
|
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
|
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
|
|
FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
|
|
}
|
|
|
|
/* Configure the values in handle. */
|
|
switch (dataFormat)
|
|
{
|
|
case (uint8_t)kFLEXIO_SPI_8bitMsb:
|
|
dataMode = (8UL * 2UL - 1UL) << 8U;
|
|
bytesPerFrame = 1U;
|
|
direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
|
|
case (uint8_t)kFLEXIO_SPI_8bitLsb:
|
|
dataMode = (8UL * 2UL - 1UL) << 8U;
|
|
bytesPerFrame = 1U;
|
|
direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
|
|
case (uint8_t)kFLEXIO_SPI_16bitMsb:
|
|
dataMode = (16UL * 2UL - 1UL) << 8U;
|
|
bytesPerFrame = 2U;
|
|
direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
|
|
case (uint8_t)kFLEXIO_SPI_16bitLsb:
|
|
dataMode = (16UL * 2UL - 1UL) << 8U;
|
|
bytesPerFrame = 2U;
|
|
direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
|
|
case (uint8_t)kFLEXIO_SPI_32bitMsb:
|
|
dataMode = (32UL * 2UL - 1UL) << 8U;
|
|
bytesPerFrame = 4U;
|
|
direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
|
|
case (uint8_t)kFLEXIO_SPI_32bitLsb:
|
|
dataMode = (32UL * 2UL - 1UL) << 8U;
|
|
bytesPerFrame = 4U;
|
|
direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
|
|
default:
|
|
dataMode = (8UL * 2UL - 1UL) << 8U;
|
|
bytesPerFrame = 1U;
|
|
direction = kFLEXIO_SPI_MsbFirst;
|
|
assert(true);
|
|
break;
|
|
}
|
|
|
|
dataMode |= timerCmp;
|
|
|
|
/* Transfer size should be bytesPerFrame divisible. */
|
|
if ((xfer->dataSize % bytesPerFrame) != 0U)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Configure transfer size. */
|
|
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
|
|
|
while (xfer->dataSize != 0U)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
#if SPI_RETRY_TIMES
|
|
waitTimes = SPI_RETRY_TIMES;
|
|
while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) &&
|
|
(0U != --waitTimes))
|
|
#else
|
|
while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag))
|
|
#endif
|
|
{
|
|
}
|
|
#if SPI_RETRY_TIMES
|
|
if (waitTimes == 0U)
|
|
{
|
|
return kStatus_FLEXIO_SPI_Timeout;
|
|
}
|
|
#endif
|
|
if (xfer->txData != NULL)
|
|
{
|
|
/* Transmit data and update tx size/buff. */
|
|
if (bytesPerFrame == 1U)
|
|
{
|
|
tmpData = (uint32_t) * (xfer->txData);
|
|
xfer->txData++;
|
|
}
|
|
else if (bytesPerFrame == 2U)
|
|
{
|
|
if (direction == kFLEXIO_SPI_MsbFirst)
|
|
{
|
|
tmpData = (uint32_t)(xfer->txData[0]) << 8U;
|
|
tmpData += (uint32_t)xfer->txData[1];
|
|
}
|
|
else
|
|
{
|
|
tmpData = (uint32_t)(xfer->txData[1]) << 8U;
|
|
tmpData += (uint32_t)xfer->txData[0];
|
|
}
|
|
xfer->txData += 2U;
|
|
}
|
|
else
|
|
{
|
|
if (direction == kFLEXIO_SPI_MsbFirst)
|
|
{
|
|
tmpData = (uint32_t)(xfer->txData[0]) << 24U;
|
|
tmpData += (uint32_t)(xfer->txData[1]) << 16U;
|
|
tmpData += (uint32_t)(xfer->txData[2]) << 8U;
|
|
tmpData += (uint32_t)xfer->txData[3];
|
|
}
|
|
else
|
|
{
|
|
tmpData = (uint32_t)(xfer->txData[3]) << 24U;
|
|
tmpData += (uint32_t)(xfer->txData[2]) << 16U;
|
|
tmpData += (uint32_t)(xfer->txData[1]) << 8U;
|
|
tmpData += (uint32_t)xfer->txData[0];
|
|
}
|
|
xfer->txData += 4U;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
}
|
|
|
|
xfer->dataSize -= bytesPerFrame;
|
|
|
|
FLEXIO_SPI_WriteData(base, direction, tmpData);
|
|
|
|
#if SPI_RETRY_TIMES
|
|
waitTimes = SPI_RETRY_TIMES;
|
|
while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) &&
|
|
(0U != --waitTimes))
|
|
#else
|
|
while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag))
|
|
#endif
|
|
{
|
|
}
|
|
#if SPI_RETRY_TIMES
|
|
if (waitTimes == 0U)
|
|
{
|
|
return kStatus_FLEXIO_SPI_Timeout;
|
|
}
|
|
#endif
|
|
tmpData = FLEXIO_SPI_ReadData(base, direction);
|
|
|
|
if (xfer->rxData != NULL)
|
|
{
|
|
if (bytesPerFrame == 1U)
|
|
{
|
|
*xfer->rxData = (uint8_t)tmpData;
|
|
}
|
|
else if (bytesPerFrame == 2U)
|
|
{
|
|
if (direction == kFLEXIO_SPI_LsbFirst)
|
|
{
|
|
*xfer->rxData = (uint8_t)(tmpData >> 8);
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)tmpData;
|
|
}
|
|
else
|
|
{
|
|
*xfer->rxData = (uint8_t)tmpData;
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)(tmpData >> 8);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (direction == kFLEXIO_SPI_LsbFirst)
|
|
{
|
|
*xfer->rxData = (uint8_t)(tmpData >> 24U);
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)(tmpData >> 16U);
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)(tmpData >> 8U);
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)tmpData;
|
|
}
|
|
else
|
|
{
|
|
*xfer->rxData = (uint8_t)tmpData;
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)(tmpData >> 8U);
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)(tmpData >> 16U);
|
|
xfer->rxData++;
|
|
*xfer->rxData = (uint8_t)(tmpData >> 24U);
|
|
}
|
|
}
|
|
xfer->rxData++;
|
|
}
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Initializes the FlexIO SPI Master handle, which is used in transactional functions.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
|
|
* param callback The callback function.
|
|
* param userData The parameter of the callback function.
|
|
* retval kStatus_Success Successfully create the handle.
|
|
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
|
|
*/
|
|
status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base,
|
|
flexio_spi_master_handle_t *handle,
|
|
flexio_spi_master_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
|
|
|
|
/* Zero the handle. */
|
|
(void)memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Register callback and userData. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
/* Clear pending NVIC IRQ before enable NVIC IRQ. */
|
|
NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
|
|
/* Enable interrupt in NVIC. */
|
|
(void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ);
|
|
}
|
|
|
|
/*!
|
|
* brief Master transfer data using IRQ.
|
|
*
|
|
* This function sends data using IRQ. This is a non-blocking function, which returns
|
|
* right away. When all data is sent out/received, the callback function is called.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
|
|
* param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
|
|
* retval kStatus_Success Successfully start a transfer.
|
|
* retval kStatus_InvalidArgument Input argument is invalid.
|
|
* retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer.
|
|
*/
|
|
status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
|
|
flexio_spi_master_handle_t *handle,
|
|
flexio_spi_transfer_t *xfer)
|
|
{
|
|
assert(handle != NULL);
|
|
assert(xfer != NULL);
|
|
|
|
uint32_t dataMode = 0;
|
|
uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
|
|
uint32_t tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
|
|
|
|
timerCmp &= 0x00FFU;
|
|
|
|
/* Check if SPI is busy. */
|
|
if (handle->state == (uint32_t)kFLEXIO_SPI_Busy)
|
|
{
|
|
return kStatus_FLEXIO_SPI_Busy;
|
|
}
|
|
|
|
/* Check if the argument is legal. */
|
|
if ((xfer->txData == NULL) && (xfer->rxData == NULL))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0
|
|
enables when tx shifter is written and disables when timer compare. The timer compare event causes the
|
|
transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is
|
|
disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if
|
|
software writes the tx register upon the detection of tx register empty event, the timer enable condition
|
|
is triggered again, then the CS signal can remain low until software no longer writes the tx register. */
|
|
if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
|
|
{
|
|
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
|
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
|
|
FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
|
|
}
|
|
else
|
|
{
|
|
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
|
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
|
|
FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
|
|
}
|
|
|
|
/* Configure the values in handle */
|
|
switch (dataFormat)
|
|
{
|
|
case (uint8_t)kFLEXIO_SPI_8bitMsb:
|
|
dataMode = (8UL * 2UL - 1UL) << 8U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_8bitLsb:
|
|
dataMode = (8UL * 2UL - 1UL) << 8U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_16bitMsb:
|
|
dataMode = (16UL * 2UL - 1UL) << 8U;
|
|
handle->bytePerFrame = 2U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_16bitLsb:
|
|
dataMode = (16UL * 2UL - 1UL) << 8U;
|
|
handle->bytePerFrame = 2U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_32bitMsb:
|
|
dataMode = (32UL * 2UL - 1UL) << 8U;
|
|
handle->bytePerFrame = 4U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_32bitLsb:
|
|
dataMode = (32UL * 2UL - 1UL) << 8U;
|
|
handle->bytePerFrame = 4U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
default:
|
|
dataMode = (8UL * 2UL - 1UL) << 8U;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
assert(true);
|
|
break;
|
|
}
|
|
|
|
dataMode |= timerCmp;
|
|
|
|
/* Transfer size should be bytesPerFrame divisible. */
|
|
if ((xfer->dataSize % handle->bytePerFrame) != 0U)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Configure transfer size. */
|
|
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
|
|
|
handle->state = (uint32_t)kFLEXIO_SPI_Busy;
|
|
handle->txData = xfer->txData;
|
|
handle->rxData = xfer->rxData;
|
|
handle->rxRemainingBytes = xfer->dataSize;
|
|
|
|
/* Save total transfer size. */
|
|
handle->transferSize = xfer->dataSize;
|
|
|
|
/* Send first byte of data to trigger the rx interrupt. */
|
|
if (handle->txData != NULL)
|
|
{
|
|
/* Transmit data and update tx size/buff. */
|
|
if (handle->bytePerFrame == 1U)
|
|
{
|
|
tmpData = (uint32_t) * (handle->txData);
|
|
handle->txData++;
|
|
}
|
|
else if (handle->bytePerFrame == 2U)
|
|
{
|
|
if (handle->direction == kFLEXIO_SPI_MsbFirst)
|
|
{
|
|
tmpData = (uint32_t)(handle->txData[0]) << 8U;
|
|
tmpData += (uint32_t)handle->txData[1];
|
|
}
|
|
else
|
|
{
|
|
tmpData = (uint32_t)(handle->txData[1]) << 8U;
|
|
tmpData += (uint32_t)handle->txData[0];
|
|
}
|
|
handle->txData += 2U;
|
|
}
|
|
else
|
|
{
|
|
if (handle->direction == kFLEXIO_SPI_MsbFirst)
|
|
{
|
|
tmpData = (uint32_t)(handle->txData[0]) << 24U;
|
|
tmpData += (uint32_t)(handle->txData[1]) << 16U;
|
|
tmpData += (uint32_t)(handle->txData[2]) << 8U;
|
|
tmpData += (uint32_t)handle->txData[3];
|
|
}
|
|
else
|
|
{
|
|
tmpData = (uint32_t)(handle->txData[3]) << 24U;
|
|
tmpData += (uint32_t)(handle->txData[2]) << 16U;
|
|
tmpData += (uint32_t)(handle->txData[1]) << 8U;
|
|
tmpData += (uint32_t)handle->txData[0];
|
|
}
|
|
handle->txData += 4U;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tmpData = FLEXIO_SPI_DUMMYDATA;
|
|
}
|
|
|
|
handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame;
|
|
|
|
FLEXIO_SPI_WriteData(base, handle->direction, tmpData);
|
|
|
|
/* Enable transmit and receive interrupt to handle rx. */
|
|
FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
|
|
|
|
if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
|
|
{
|
|
FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the data transfer status which used IRQ.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
|
|
* param count Number of bytes transferred so far by the non-blocking transaction.
|
|
* retval kStatus_InvalidArgument count is Invalid.
|
|
* retval kStatus_Success Successfully return the count.
|
|
*/
|
|
status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
if (NULL == count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Return remaing bytes in different cases. */
|
|
if (handle->rxData != NULL)
|
|
{
|
|
*count = handle->transferSize - handle->rxRemainingBytes;
|
|
}
|
|
else
|
|
{
|
|
*count = handle->transferSize - handle->txRemainingBytes;
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief Aborts the master data transfer, which used IRQ.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
|
|
*/
|
|
void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
|
|
FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
|
|
|
|
/* Transfer finished, set the state to idle. */
|
|
handle->state = (uint32_t)kFLEXIO_SPI_Idle;
|
|
|
|
/* Clear the internal state. */
|
|
handle->rxRemainingBytes = 0;
|
|
handle->txRemainingBytes = 0;
|
|
}
|
|
|
|
/*!
|
|
* brief FlexIO SPI master IRQ handler function.
|
|
*
|
|
* param spiType Pointer to the FLEXIO_SPI_Type structure.
|
|
* param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state.
|
|
*/
|
|
void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
|
|
{
|
|
assert(spiHandle != NULL);
|
|
|
|
flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
|
|
FLEXIO_SPI_Type *base;
|
|
uint32_t status;
|
|
|
|
if (handle->state == (uint32_t)kFLEXIO_SPI_Idle)
|
|
{
|
|
return;
|
|
}
|
|
|
|
base = (FLEXIO_SPI_Type *)spiType;
|
|
status = FLEXIO_SPI_GetStatusFlags(base);
|
|
|
|
/* Receive interrupt. */
|
|
if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U)
|
|
{
|
|
FLEXIO_SPI_TransferSendTransaction(base, handle);
|
|
return;
|
|
}
|
|
|
|
/* Handle rx. */
|
|
if (handle->rxRemainingBytes != 0U)
|
|
{
|
|
FLEXIO_SPI_TransferReceiveTransaction(base, handle);
|
|
}
|
|
|
|
/* Handle tx. */
|
|
if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U))
|
|
{
|
|
FLEXIO_SPI_TransferSendTransaction(base, handle);
|
|
}
|
|
|
|
/* All the transfer finished. */
|
|
if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
|
|
{
|
|
FLEXIO_SPI_MasterTransferAbort(base, handle);
|
|
if (handle->callback != NULL)
|
|
{
|
|
(handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
* param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
|
|
* param callback The callback function.
|
|
* param userData The parameter of the callback function.
|
|
* retval kStatus_Success Successfully create the handle.
|
|
* retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
|
|
*/
|
|
status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base,
|
|
flexio_spi_slave_handle_t *handle,
|
|
flexio_spi_slave_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
|
|
|
|
/* Zero the handle. */
|
|
(void)memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Register callback and userData. */
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
|
|
/* Clear pending NVIC IRQ before enable NVIC IRQ. */
|
|
NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
|
|
/* Enable interrupt in NVIC. */
|
|
(void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]);
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ);
|
|
}
|
|
|
|
/*!
|
|
* brief Slave transfer data using IRQ.
|
|
*
|
|
* This function sends data using IRQ. This is a non-blocking function, which returns
|
|
* right away. When all data is sent out/received, the callback function is called.
|
|
* param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
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*
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* param base Pointer to the FLEXIO_SPI_Type structure.
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* param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t.
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* retval kStatus_Success Successfully start a transfer.
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* retval kStatus_InvalidArgument Input argument is invalid.
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* retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer.
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*/
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status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base,
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flexio_spi_slave_handle_t *handle,
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flexio_spi_transfer_t *xfer)
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{
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assert(handle != NULL);
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assert(xfer != NULL);
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|
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uint32_t dataMode = 0;
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uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
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|
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/* Check if SPI is busy. */
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if (handle->state == (uint32_t)kFLEXIO_SPI_Busy)
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{
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return kStatus_FLEXIO_SPI_Busy;
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}
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|
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/* Check if the argument is legal. */
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if ((xfer->txData == NULL) && (xfer->rxData == NULL))
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{
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return kStatus_InvalidArgument;
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}
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|
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|
/* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */
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/* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and
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before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode,
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timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode,
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tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */
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FLEXIO_SPI_FlushShifters(base);
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if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
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{
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base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
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}
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else
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|
{
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|
if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) ==
|
|
FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive))
|
|
{
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|
base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
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(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
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FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
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|
}
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|
else
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|
{
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base->flexioBase->TIMCFG[base->timerIndex[0]] =
|
|
(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
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FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
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|
}
|
|
}
|
|
|
|
/* Configure the values in handle */
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|
switch (dataFormat)
|
|
{
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|
case (uint8_t)kFLEXIO_SPI_8bitMsb:
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dataMode = 8U * 2U - 1U;
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handle->bytePerFrame = 1U;
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handle->direction = kFLEXIO_SPI_MsbFirst;
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break;
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case (uint8_t)kFLEXIO_SPI_8bitLsb:
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dataMode = 8U * 2U - 1U;
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handle->bytePerFrame = 1U;
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handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
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case (uint8_t)kFLEXIO_SPI_16bitMsb:
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dataMode = 16U * 2U - 1U;
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handle->bytePerFrame = 2U;
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|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_16bitLsb:
|
|
dataMode = 16U * 2U - 1U;
|
|
handle->bytePerFrame = 2U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_32bitMsb:
|
|
dataMode = 32UL * 2UL - 1UL;
|
|
handle->bytePerFrame = 4U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
break;
|
|
case (uint8_t)kFLEXIO_SPI_32bitLsb:
|
|
dataMode = 32UL * 2UL - 1UL;
|
|
handle->bytePerFrame = 4U;
|
|
handle->direction = kFLEXIO_SPI_LsbFirst;
|
|
break;
|
|
default:
|
|
dataMode = 8UL * 2UL - 1UL;
|
|
handle->bytePerFrame = 1U;
|
|
handle->direction = kFLEXIO_SPI_MsbFirst;
|
|
assert(true);
|
|
break;
|
|
}
|
|
|
|
/* Transfer size should be bytesPerFrame divisible. */
|
|
if ((xfer->dataSize % handle->bytePerFrame) != 0U)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Configure transfer size. */
|
|
base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
|
|
|
|
handle->state = (uint32_t)kFLEXIO_SPI_Busy;
|
|
handle->txData = xfer->txData;
|
|
handle->rxData = xfer->rxData;
|
|
handle->txRemainingBytes = xfer->dataSize;
|
|
handle->rxRemainingBytes = xfer->dataSize;
|
|
|
|
/* Save total transfer size. */
|
|
handle->transferSize = xfer->dataSize;
|
|
|
|
/* Enable transmit and receive interrupt to handle tx and rx. */
|
|
FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
|
|
FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
/*!
|
|
* brief FlexIO SPI slave IRQ handler function.
|
|
*
|
|
* param spiType Pointer to the FLEXIO_SPI_Type structure.
|
|
* param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state.
|
|
*/
|
|
void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle)
|
|
{
|
|
assert(spiHandle != NULL);
|
|
|
|
flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle;
|
|
FLEXIO_SPI_Type *base;
|
|
uint32_t status;
|
|
|
|
if (handle->state == (uint32_t)kFLEXIO_SPI_Idle)
|
|
{
|
|
return;
|
|
}
|
|
|
|
base = (FLEXIO_SPI_Type *)spiType;
|
|
status = FLEXIO_SPI_GetStatusFlags(base);
|
|
|
|
/* Handle tx. */
|
|
if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U))
|
|
{
|
|
FLEXIO_SPI_TransferSendTransaction(base, handle);
|
|
}
|
|
|
|
/* Handle rx. */
|
|
if (((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) && (handle->rxRemainingBytes != 0U))
|
|
{
|
|
FLEXIO_SPI_TransferReceiveTransaction(base, handle);
|
|
}
|
|
|
|
/* All the transfer finished. */
|
|
if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U))
|
|
{
|
|
FLEXIO_SPI_SlaveTransferAbort(base, handle);
|
|
if (handle->callback != NULL)
|
|
{
|
|
(handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Flush tx/rx shifters.
|
|
*
|
|
* param base Pointer to the FLEXIO_SPI_Type structure.
|
|
*/
|
|
void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base)
|
|
{
|
|
/* Disable then re-enable to flush the tx shifter. */
|
|
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK;
|
|
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
|
|
/* Read to flush the rx shifter. */
|
|
(void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]];
|
|
}
|