566 lines
20 KiB
C
566 lines
20 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2020, 2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexio_spi_edma.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma"
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#endif
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/*<! Structure definition for spi_edma_private_handle_t. The structure is private. */
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typedef struct _flexio_spi_master_edma_private_handle
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{
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FLEXIO_SPI_Type *base;
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flexio_spi_master_edma_handle_t *handle;
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} flexio_spi_master_edma_private_handle_t;
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief EDMA callback function for FLEXIO SPI send transfer.
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*
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* @param handle EDMA handle pointer.
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* @param param Callback function parameter.
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*/
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static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
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/*!
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* @brief EDMA callback function for FLEXIO SPI receive transfer.
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*
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* @param handle EDMA handle pointer.
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* @param param Callback function parameter.
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*/
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static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
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/*!
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* @brief EDMA config for FLEXIO SPI transfer.
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*
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* @param base pointer to FLEXIO_SPI_Type structure.
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* @param handle pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
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* @param xfer Pointer to flexio spi transfer structure.
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* @retval kStatus_Success Successfully create the handle.
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* @retval kStatus_InvalidArgument The transfer size is not supported.
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*/
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static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
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flexio_spi_master_edma_handle_t *handle,
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flexio_spi_transfer_t *xfer);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Dummy data used to send */
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static const uint32_t s_dummyData = FLEXIO_SPI_DUMMYDATA;
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/*< @brief user configurable flexio spi handle count. */
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#define FLEXIO_SPI_HANDLE_COUNT 2
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/*<! Private handle only used for internally. */
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static flexio_spi_master_edma_private_handle_t s_edmaPrivateHandle[FLEXIO_SPI_HANDLE_COUNT];
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/*******************************************************************************
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* Code
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******************************************************************************/
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static void FLEXIO_SPI_TxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
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{
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tcds = tcds;
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flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
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/* Disable Tx DMA */
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if (transferDone)
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{
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FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, false);
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/* change the state */
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spiPrivateHandle->handle->txInProgress = false;
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/* All finished, call the callback */
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if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false))
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{
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if (spiPrivateHandle->handle->callback != NULL)
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{
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(spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success,
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spiPrivateHandle->handle->userData);
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}
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}
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}
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}
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static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
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{
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tcds = tcds;
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flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param;
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if (transferDone)
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{
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/* Disable Rx dma */
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FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, false);
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/* change the state */
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spiPrivateHandle->handle->rxInProgress = false;
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/* All finished, call the callback */
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if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false))
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{
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if (spiPrivateHandle->handle->callback != NULL)
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{
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(spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success,
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spiPrivateHandle->handle->userData);
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}
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}
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}
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}
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static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
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flexio_spi_master_edma_handle_t *handle,
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flexio_spi_transfer_t *xfer)
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{
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edma_transfer_config_t xferConfig = {0};
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flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst;
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uint8_t bytesPerFrame;
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uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
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/* Configure the values in handle. */
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switch (dataFormat)
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{
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case (uint8_t)kFLEXIO_SPI_8bitMsb:
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bytesPerFrame = 1U;
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direction = kFLEXIO_SPI_MsbFirst;
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break;
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case (uint8_t)kFLEXIO_SPI_8bitLsb:
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bytesPerFrame = 1U;
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direction = kFLEXIO_SPI_LsbFirst;
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break;
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case (uint8_t)kFLEXIO_SPI_16bitMsb:
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bytesPerFrame = 2U;
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direction = kFLEXIO_SPI_MsbFirst;
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break;
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case (uint8_t)kFLEXIO_SPI_16bitLsb:
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bytesPerFrame = 2U;
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direction = kFLEXIO_SPI_LsbFirst;
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break;
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case (uint8_t)kFLEXIO_SPI_32bitMsb:
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bytesPerFrame = 4U;
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direction = kFLEXIO_SPI_MsbFirst;
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break;
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case (uint8_t)kFLEXIO_SPI_32bitLsb:
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bytesPerFrame = 4U;
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direction = kFLEXIO_SPI_LsbFirst;
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break;
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default:
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bytesPerFrame = 1U;
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direction = kFLEXIO_SPI_MsbFirst;
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assert(true);
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break;
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}
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/* Transfer size should be bytesPerFrame divisible. */
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if ((xfer->dataSize % bytesPerFrame) != 0U)
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{
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return kStatus_InvalidArgument;
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}
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/* Save total transfer size. */
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handle->transferSize = xfer->dataSize;
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/* Configure tx transfer EDMA. */
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xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
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xferConfig.destOffset = 0;
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if (bytesPerFrame == 1U)
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{
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xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
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xferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
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xferConfig.minorLoopBytes = 1U;
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}
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else if (bytesPerFrame == 2U)
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{
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if (direction == kFLEXIO_SPI_MsbFirst)
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{
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xferConfig.destAddr -= 1U;
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}
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xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes;
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xferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
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xferConfig.minorLoopBytes = 2U;
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}
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else
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{
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if (direction == kFLEXIO_SPI_MsbFirst)
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{
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xferConfig.destAddr -= 3U;
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}
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xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes;
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xferConfig.destTransferSize = kEDMA_TransferSize4Bytes;
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xferConfig.minorLoopBytes = 4U;
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}
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/* Configure DMA channel. */
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if (xfer->txData != NULL)
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{
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xferConfig.srcOffset = (int16_t)bytesPerFrame;
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xferConfig.srcAddr = (uint32_t)(xfer->txData);
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}
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else
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{
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/* Disable the source increasement and source set to dummyData. */
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xferConfig.srcOffset = 0;
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xferConfig.srcAddr = (uint32_t)(&s_dummyData);
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}
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xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes);
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/* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */
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handle->nbytes = (uint8_t)xferConfig.minorLoopBytes;
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if (handle->txHandle != NULL)
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{
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(void)EDMA_SubmitTransfer(handle->txHandle, &xferConfig);
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}
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/* Configure rx transfer EDMA. */
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if (xfer->rxData != NULL)
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{
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xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction);
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if (bytesPerFrame == 2U)
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{
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if (direction == kFLEXIO_SPI_LsbFirst)
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{
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xferConfig.srcAddr -= 1U;
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}
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}
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else if (bytesPerFrame == 4U)
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{
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if (direction == kFLEXIO_SPI_LsbFirst)
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{
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xferConfig.srcAddr -= 3U;
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}
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}
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else
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{
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}
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xferConfig.srcOffset = 0;
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xferConfig.destAddr = (uint32_t)(xfer->rxData);
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xferConfig.destOffset = (int16_t)bytesPerFrame;
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(void)EDMA_SubmitTransfer(handle->rxHandle, &xferConfig);
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handle->rxInProgress = true;
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FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, true);
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EDMA_StartTransfer(handle->rxHandle);
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}
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/* Always start tx transfer. */
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if (handle->txHandle != NULL)
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{
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handle->txInProgress = true;
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FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, true);
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EDMA_StartTransfer(handle->txHandle);
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}
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return kStatus_Success;
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}
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/*!
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* brief Initializes the FlexIO SPI master eDMA handle.
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*
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* This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master
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* transactional
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* APIs.
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* For a specified FlexIO SPI instance, call this API once to get the initialized handle.
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*
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* param base Pointer to FLEXIO_SPI_Type structure.
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* param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
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* param callback SPI callback, NULL means no callback.
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* param userData callback function parameter.
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* param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer.
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* param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer.
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* retval kStatus_Success Successfully create the handle.
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* retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range.
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*/
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status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base,
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flexio_spi_master_edma_handle_t *handle,
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flexio_spi_master_edma_transfer_callback_t callback,
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void *userData,
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edma_handle_t *txHandle,
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edma_handle_t *rxHandle)
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{
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assert(handle != NULL);
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uint8_t index = 0;
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/* Find the an empty handle pointer to store the handle. */
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for (index = 0U; index < (uint8_t)FLEXIO_SPI_HANDLE_COUNT; index++)
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{
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if (s_edmaPrivateHandle[index].base == NULL)
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{
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s_edmaPrivateHandle[index].base = base;
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s_edmaPrivateHandle[index].handle = handle;
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break;
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}
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}
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if (index == (uint16_t)FLEXIO_SPI_HANDLE_COUNT)
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{
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return kStatus_OutOfRange;
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}
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/* Set spi base to handle. */
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handle->txHandle = txHandle;
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handle->rxHandle = rxHandle;
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/* Register callback and userData. */
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handle->callback = callback;
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handle->userData = userData;
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/* Set SPI state to idle. */
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handle->txInProgress = false;
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handle->rxInProgress = false;
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/* Install callback for Tx/Rx dma channel. */
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if (handle->txHandle != NULL)
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{
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EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]);
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}
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if (handle->rxHandle != NULL)
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{
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EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]);
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}
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return kStatus_Success;
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}
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/*!
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* brief Performs a non-blocking FlexIO SPI transfer using eDMA.
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*
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* note This interface returns immediately after transfer initiates. Call
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* FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check
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* whether the FlexIO SPI transfer is finished.
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*
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* param base Pointer to FLEXIO_SPI_Type structure.
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* param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state.
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* param xfer Pointer to FlexIO SPI transfer structure.
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* retval kStatus_Success Successfully start a transfer.
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* retval kStatus_InvalidArgument Input argument is invalid.
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* retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
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*/
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status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base,
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flexio_spi_master_edma_handle_t *handle,
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flexio_spi_transfer_t *xfer)
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{
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assert(handle != NULL);
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assert(xfer != NULL);
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uint32_t dataMode = 0;
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uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]];
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uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
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timerCmp &= 0x00FFU;
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/* Check if the device is busy. */
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if ((handle->txInProgress) || (handle->rxInProgress))
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{
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return kStatus_FLEXIO_SPI_Busy;
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}
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/* Check if input parameter invalid. */
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if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
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{
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return kStatus_InvalidArgument;
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}
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/* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0
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enables when tx shifter is written and disables when timer compare. The timer compare event causes the
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transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is
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disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if
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software writes the tx register upon the detection of tx register empty event, the timer enable condition
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is triggered again, then the CS signal can remain low until software no longer writes the tx register. */
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if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
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{
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base->flexioBase->TIMCFG[base->timerIndex[0]] =
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(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
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FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled);
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}
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else
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{
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base->flexioBase->TIMCFG[base->timerIndex[0]] =
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(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) |
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FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable);
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}
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/* configure data mode. */
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if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
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{
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dataMode = (8UL * 2UL - 1UL) << 8U;
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}
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else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
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{
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dataMode = (16UL * 2UL - 1UL) << 8U;
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}
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else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
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{
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dataMode = (32UL * 2UL - 1UL) << 8U;
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}
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else
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{
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dataMode = (8UL * 2UL - 1UL) << 8U;
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}
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dataMode |= timerCmp;
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base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
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return FLEXIO_SPI_EDMAConfig(base, handle, xfer);
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}
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/*!
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* brief Gets the remaining bytes for FlexIO SPI eDMA transfer.
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*
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* param base Pointer to FLEXIO_SPI_Type structure.
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* param handle FlexIO SPI eDMA handle pointer.
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* param count Number of bytes transferred so far by the non-blocking transaction.
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*/
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status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base,
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flexio_spi_master_edma_handle_t *handle,
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size_t *count)
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{
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assert(handle != NULL);
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if (NULL == count)
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{
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return kStatus_InvalidArgument;
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}
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if (handle->rxInProgress)
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{
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*count =
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(handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(
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handle->rxHandle->base, handle->rxHandle->channel));
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}
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else
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{
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*count =
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(handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(
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handle->txHandle->base, handle->txHandle->channel));
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}
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return kStatus_Success;
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}
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/*!
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* brief Aborts a FlexIO SPI transfer using eDMA.
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*
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* param base Pointer to FLEXIO_SPI_Type structure.
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* param handle FlexIO SPI eDMA handle pointer.
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*/
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void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle)
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{
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assert(handle != NULL);
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/* Disable dma. */
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EDMA_AbortTransfer(handle->txHandle);
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EDMA_AbortTransfer(handle->rxHandle);
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/* Disable DMA enable bit. */
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FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_DmaAllEnable, false);
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/* Set the handle state. */
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handle->txInProgress = false;
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handle->rxInProgress = false;
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}
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|
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/*!
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* brief Performs a non-blocking FlexIO SPI transfer using eDMA.
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*
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* note This interface returns immediately after transfer initiates. Call
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* FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and
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* check whether the FlexIO SPI transfer is finished.
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*
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* param base Pointer to FLEXIO_SPI_Type structure.
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* param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state.
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* param xfer Pointer to FlexIO SPI transfer structure.
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* retval kStatus_Success Successfully start a transfer.
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* retval kStatus_InvalidArgument Input argument is invalid.
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* retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer.
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*/
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status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base,
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flexio_spi_slave_edma_handle_t *handle,
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flexio_spi_transfer_t *xfer)
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{
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assert(handle != NULL);
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assert(xfer != NULL);
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uint32_t dataMode = 0U;
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uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags);
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/* Check if the device is busy. */
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if ((handle->txInProgress) || (handle->rxInProgress))
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{
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return kStatus_FLEXIO_SPI_Busy;
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}
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/* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */
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/* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and
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before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode,
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timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode,
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tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */
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FLEXIO_SPI_FlushShifters(base);
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if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
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{
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base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
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}
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else
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{
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if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) ==
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FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive))
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{
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base->flexioBase->TIMCFG[base->timerIndex[0]] =
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(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
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FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
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}
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else
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{
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base->flexioBase->TIMCFG[base->timerIndex[0]] =
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(base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) |
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FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge);
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}
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}
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/* Check if input parameter invalid. */
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if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U))
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{
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return kStatus_InvalidArgument;
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}
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/* configure data mode. */
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if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb))
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{
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dataMode = 8U * 2U - 1U;
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}
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else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb))
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{
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dataMode = 16U * 2U - 1U;
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}
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else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb))
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{
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dataMode = 32UL * 2UL - 1UL;
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}
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else
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{
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dataMode = 8U * 2U - 1U;
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}
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base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode;
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return FLEXIO_SPI_EDMAConfig(base, handle, xfer);
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}
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