151 lines
4.8 KiB
C
151 lines
4.8 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_pit.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.pit"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address to be used to gate or ungate the module clock
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*
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* @param base PIT peripheral base address
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*
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* @return The PIT instance
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*/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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static uint32_t PIT_GetInstance(PIT_Type *base);
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to PIT bases for each instance. */
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static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
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/*! @brief Pointers to PIT clocks for each instance. */
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static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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static uint32_t PIT_GetInstance(PIT_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
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{
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if (s_pitBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_pitBases));
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return instance;
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}
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*!
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* brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations.
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*
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* note This API should be called at the beginning of the application using the PIT driver.
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*
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* param base PIT peripheral base address
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* param config Pointer to the user's PIT config structure
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*/
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void PIT_Init(PIT_Type *base, const pit_config_t *config)
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{
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assert(NULL != config);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate the PIT clock*/
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CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
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/* Enable PIT timers */
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base->MCR &= ~PIT_MCR_MDIS_MASK;
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#endif
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#if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT)
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/* Clear all status bits for all channels to make sure the status of all TCTRL registers is clean. */
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for (uint8_t i = 0U; i < (uint32_t)FSL_FEATURE_PIT_TIMER_COUNT; i++)
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{
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base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK);
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}
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#endif /* FSL_FEATURE_PIT_TIMER_COUNT */
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/* Config timer operation when in debug mode */
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if (true == config->enableRunInDebug)
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{
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base->MCR &= ~PIT_MCR_FRZ_MASK;
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}
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else
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{
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base->MCR |= PIT_MCR_FRZ_MASK;
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}
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}
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/*!
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* brief Gates the PIT clock and disables the PIT module.
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*
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* param base PIT peripheral base address
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*/
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void PIT_Deinit(PIT_Type *base)
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{
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#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS
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/* Disable PIT timers */
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base->MCR |= PIT_MCR_MDIS_MASK;
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#endif
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate the PIT clock*/
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CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
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/*!
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* brief Reads the current lifetime counter value.
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*
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* The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together.
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* Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer.
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* The period of lifetime timer is equal to the "period of timer 0 * period of timer 1".
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* For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit
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* has the value of timer 0.
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*
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* param base PIT peripheral base address
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*
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* return Current lifetime timer value
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*/
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uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
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{
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uint32_t valueH = 0U;
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uint32_t valueL = 0U;
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/* LTMR64H should be read before LTMR64L */
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valueH = base->LTMR64H;
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valueL = base->LTMR64L;
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return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
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}
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#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
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