230 lines
7.2 KiB
C
230 lines
7.2 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_xbara.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.xbara"
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#endif
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/* Macros for entire XBARA_CTRL register. */
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#define XBARA_CTRLx(base, index) (((volatile uint16_t *)(&((base)->CTRL0)))[(index)])
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typedef union
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{
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uint8_t _u8[2];
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uint16_t _u16;
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} xbara_u8_u16_t;
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the XBARA instance from peripheral base address.
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*
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* @param base XBARA peripheral base address.
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* @return XBARA instance.
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*/
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static uint32_t XBARA_GetInstance(XBARA_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* Array of XBARA peripheral base address. */
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static XBARA_Type *const s_xbaraBases[] = XBARA_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Array of XBARA clock name. */
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static const clock_ip_name_t s_xbaraClock[] = XBARA_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t XBARA_GetInstance(XBARA_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_xbaraBases); instance++)
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{
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if (s_xbaraBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_xbaraBases));
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return instance;
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}
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/*!
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* brief Initializes the XBARA module.
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*
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* This function un-gates the XBARA clock.
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*
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* param base XBARA peripheral address.
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*/
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void XBARA_Init(XBARA_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable XBARA module clock. */
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CLOCK_EnableClock(s_xbaraClock[XBARA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Shuts down the XBARA module.
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*
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* This function disables XBARA clock.
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*
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* param base XBARA peripheral address.
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*/
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void XBARA_Deinit(XBARA_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable XBARA module clock. */
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CLOCK_DisableClock(s_xbaraClock[XBARA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal.
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*
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* This function connects the XBARA input to the selected XBARA output.
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* If more than one XBARA module is available, only the inputs and outputs from the same module
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* can be connected.
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*
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* Example:
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code
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XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18);
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endcode
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*
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* param base XBARA peripheral address.
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* param input XBARA input signal.
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* param output XBARA output signal.
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*/
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void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output)
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{
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xbara_u8_u16_t regVal;
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uint8_t byteInReg;
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uint8_t outputIndex = (uint8_t)output;
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byteInReg = outputIndex % 2U;
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regVal._u16 = XBARA_SELx(base, outputIndex);
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regVal._u8[byteInReg] = (uint8_t)input;
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XBARA_SELx(base, outputIndex) = regVal._u16;
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}
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/*!
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* brief Gets the active edge detection status.
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*
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* This function gets the active edge detect status of all XBARA_OUTs. If the
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* active edge occurs, the return value is asserted. When the interrupt or the DMA
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* functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt
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* or DMA request is asserted and 0 when the interrupt or DMA request has been
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* cleared.
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*
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* param base XBARA peripheral address.
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* return the mask of these status flag bits.
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*/
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uint32_t XBARA_GetStatusFlags(XBARA_Type *base)
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{
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uint32_t status_flag;
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status_flag = ((uint32_t)base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
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status_flag |= (((uint32_t)base->CTRL1 & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)) << 16U);
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return status_flag;
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}
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/*!
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* brief Clears the edge detection status flags of relative mask.
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*
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* param base XBARA peripheral address.
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* param mask the status flags to clear.
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*/
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void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask)
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{
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uint16_t regVal;
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/* Assign regVal to CTRL0 register's value */
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regVal = (base->CTRL0);
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/* Perform this command to avoid writing 1 into interrupt flag bits */
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regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
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/* Write 1 to interrupt flag bits corresponding to mask */
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regVal |= (uint16_t)(mask & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
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/* Write regVal value into CTRL0 register */
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base->CTRL0 = regVal;
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/* Assign regVal to CTRL1 register's value */
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regVal = (base->CTRL1);
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/* Perform this command to avoid writing 1 into interrupt flag bits */
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regVal &= (uint16_t)(~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
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/* Write 1 to interrupt flag bits corresponding to mask */
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regVal |= (uint16_t)((mask >> 16U) & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK));
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/* Write regVal value into CTRL1 register */
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base->CTRL1 = regVal;
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}
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/*!
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* brief Configures the XBARA control register.
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*
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* This function configures an XBARA control register. The active edge detection
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* and the DMA/IRQ function on the corresponding XBARA output can be set.
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*
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* Example:
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code
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xbara_control_config_t userConfig;
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userConfig.activeEdge = kXBARA_EdgeRising;
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userConfig.requestType = kXBARA_RequestInterruptEnalbe;
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XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig);
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endcode
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*
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* param base XBARA peripheral address.
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* param output XBARA output number.
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* param controlConfig Pointer to structure that keeps configuration of control register.
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*/
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void XBARA_SetOutputSignalConfig(XBARA_Type *base,
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xbar_output_signal_t output,
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const xbara_control_config_t *controlConfig)
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{
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uint8_t outputIndex = (uint8_t)output;
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uint8_t regIndex;
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uint8_t byteInReg;
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xbara_u8_u16_t regVal;
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assert(outputIndex < (uint32_t)FSL_FEATURE_XBARA_INTERRUPT_COUNT);
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regIndex = outputIndex / 2U;
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byteInReg = outputIndex % 2U;
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regVal._u16 = XBARA_CTRLx(base, regIndex);
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/* Don't clear the status flags. */
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regVal._u16 &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK));
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regVal._u8[byteInReg] = (uint8_t)(XBARA_CTRL0_EDGE0(controlConfig->activeEdge) |
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(uint16_t)(((uint32_t)controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT));
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XBARA_CTRLx(base, regIndex) = regVal._u16;
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}
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