36 lines
1022 B
C
36 lines
1022 B
C
/*
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* Copyright 2014-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2023 NXP
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef __FSL_DEVICE_REGISTERS_H__
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#define __FSL_DEVICE_REGISTERS_H__
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/*
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* Include the cpu specific register header files.
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*
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* The CPU macro should be declared in the project or makefile.
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*/
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#if (defined(CPU_MIMXRT1021CAF4A) || defined(CPU_MIMXRT1021CAF4B) || defined(CPU_MIMXRT1021CAG4A) || \
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defined(CPU_MIMXRT1021CAG4B) || defined(CPU_MIMXRT1021DAF5A) || defined(CPU_MIMXRT1021DAF5B) || \
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defined(CPU_MIMXRT1021DAG5A) || defined(CPU_MIMXRT1021DAG5B))
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#define MIMXRT1021_SERIES
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/* CMSIS-style register definitions */
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#include "MIMXRT1021.h"
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/* CPU specific feature definitions */
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#include "MIMXRT1021_features.h"
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#else
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#error "No valid CPU defined!"
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#endif
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#endif /* __FSL_DEVICE_REGISTERS_H__ */
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/*******************************************************************************
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* EOF
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******************************************************************************/
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