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<div class="title">CACHE: ARMV7-M7 CACHE Memory Controller</div> </div>
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<div class="contents">
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
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<p>The MCUXpresso SDK provides a peripheral driver for the CACHE Controller of MCUXpresso SDK devices.</p>
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<p>The CACHE driver is created to help the user more easily operate the cache memory. The APIs for basic operations are including the following three levels:</p>
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<p>1L. The L1 cache driver API. This level provides the level 1 caches controller drivers. The L1 caches are mainly integrated in the Core memory system, Cortex-M7 L1 caches, etc. For our Cortex-M4 series platforms, the L1 cache is the local memory controller (LMEM) which is not integrated in the Cortex-M4 processer memory system.</p>
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<p>2L. The L2 cache driver API. This level provides the level 2 cache controller drivers. The L2 cache could be integrated in the CORE memory system or an external L2 cache memory, PL310, etc.</p>
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<p>3L. The combined cache driver API. This level provides many APIs for combined L1 and L2 cache maintain operations. This is provided for MCUXpresso SDK drivers (DMA, ENET, USDHC, etc) which should do the cache maintenance in their transactional APIs.</p>
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<h1><a class="anchor" id="CACHEFuncGrps"></a>
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Function groups</h1>
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<h2><a class="anchor" id="L1CACHEMaintainOperation"></a>
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L1 CACHE Operation</h2>
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<p>The L1 CACHE has both code cache and data cache. This function group provides independent two groups API for both code cache and data cache. There are Enable/Disable APIs for code cache and data cache control and cache maintenance operations as Invalidate/Clean/CleanInvalidate by all and by address range.</p>
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<h2><a class="anchor" id="L2CACHEMaintainOperation"></a>
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L2 CACHE Operation</h2>
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<p>The L2 CACHE does not divide the cache to data and code. Instead, this function group provides one group cache maintenance operations as Enable/Disable/Invalidate/Clean/CleanInvalidate by all and by address range. Except the maintenance operation APIs, the L2 CACHE has it's initialization/configure API. The user can use the default configure parameter by calling L2CACHE_GetDefaultConfig() or changing the parameters as they wish. Then, call L2CACHE_Init to do the L2 CACHE initialization. After initialization, the L2 cache can then be enabled.</p>
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<p>Note: For the core external l2 Cache, the SoC usually has the control bit to select the SRAM to use as L2 Cache or normal SRAM. Make sure this selection is right when you use the L2 CACHE feature. </p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Driver version</h2></td></tr>
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<tr class="memitem:gac954b8be2bb59a983a9594c59e4b4fa5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gac954b8be2bb59a983a9594c59e4b4fa5">FSL_CACHE_DRIVER_VERSION</a>   (<a class="el" href="a00260.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 0, 4))</td></tr>
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<tr class="memdesc:gac954b8be2bb59a983a9594c59e4b4fa5"><td class="mdescLeft"> </td><td class="mdescRight">cache driver version 2.0.4. <a href="#gac954b8be2bb59a983a9594c59e4b4fa5">More...</a><br/></td></tr>
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<tr class="separator:gac954b8be2bb59a983a9594c59e4b4fa5"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Control for cortex-m7 L1 cache</h2></td></tr>
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<tr class="memitem:gaea07bb3879fa96b03f1ecaa6bf821c74"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaea07bb3879fa96b03f1ecaa6bf821c74"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gaea07bb3879fa96b03f1ecaa6bf821c74">L1CACHE_EnableICache</a> (void)</td></tr>
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<tr class="memdesc:gaea07bb3879fa96b03f1ecaa6bf821c74"><td class="mdescLeft"> </td><td class="mdescRight">Enables cortex-m7 L1 instruction cache. <br/></td></tr>
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<tr class="separator:gaea07bb3879fa96b03f1ecaa6bf821c74"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gafa6d1a14a0499342890eee0e104c8d96"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafa6d1a14a0499342890eee0e104c8d96"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gafa6d1a14a0499342890eee0e104c8d96">L1CACHE_DisableICache</a> (void)</td></tr>
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<tr class="memdesc:gafa6d1a14a0499342890eee0e104c8d96"><td class="mdescLeft"> </td><td class="mdescRight">Disables cortex-m7 L1 instruction cache. <br/></td></tr>
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<tr class="separator:gafa6d1a14a0499342890eee0e104c8d96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gabce0ccbe1684fef7eff231f3704025b6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabce0ccbe1684fef7eff231f3704025b6"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gabce0ccbe1684fef7eff231f3704025b6">L1CACHE_InvalidateICache</a> (void)</td></tr>
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<tr class="memdesc:gabce0ccbe1684fef7eff231f3704025b6"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate cortex-m7 L1 instruction cache. <br/></td></tr>
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<tr class="separator:gabce0ccbe1684fef7eff231f3704025b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaf66ed6d9a7b881ef98707861484d7530"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gaf66ed6d9a7b881ef98707861484d7530">L1CACHE_InvalidateICacheByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:gaf66ed6d9a7b881ef98707861484d7530"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate cortex-m7 L1 instruction cache by range. <a href="#gaf66ed6d9a7b881ef98707861484d7530">More...</a><br/></td></tr>
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<tr class="separator:gaf66ed6d9a7b881ef98707861484d7530"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga52d071c691c4ce9ead828e086f07f457"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga52d071c691c4ce9ead828e086f07f457"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#ga52d071c691c4ce9ead828e086f07f457">L1CACHE_EnableDCache</a> (void)</td></tr>
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<tr class="memdesc:ga52d071c691c4ce9ead828e086f07f457"><td class="mdescLeft"> </td><td class="mdescRight">Enables cortex-m7 L1 data cache. <br/></td></tr>
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<tr class="separator:ga52d071c691c4ce9ead828e086f07f457"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gae6eb154e5afc3a877aad4155cb90bca9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae6eb154e5afc3a877aad4155cb90bca9"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gae6eb154e5afc3a877aad4155cb90bca9">L1CACHE_DisableDCache</a> (void)</td></tr>
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<tr class="memdesc:gae6eb154e5afc3a877aad4155cb90bca9"><td class="mdescLeft"> </td><td class="mdescRight">Disables cortex-m7 L1 data cache. <br/></td></tr>
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<tr class="separator:gae6eb154e5afc3a877aad4155cb90bca9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad6bb45d3f9feb8ed2a63b174d204f277"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad6bb45d3f9feb8ed2a63b174d204f277"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gad6bb45d3f9feb8ed2a63b174d204f277">L1CACHE_InvalidateDCache</a> (void)</td></tr>
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<tr class="memdesc:gad6bb45d3f9feb8ed2a63b174d204f277"><td class="mdescLeft"> </td><td class="mdescRight">Invalidates cortex-m7 L1 data cache. <br/></td></tr>
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<tr class="separator:gad6bb45d3f9feb8ed2a63b174d204f277"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab1dcfc930ee90724a807f69428a1f269"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab1dcfc930ee90724a807f69428a1f269"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gab1dcfc930ee90724a807f69428a1f269">L1CACHE_CleanDCache</a> (void)</td></tr>
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<tr class="memdesc:gab1dcfc930ee90724a807f69428a1f269"><td class="mdescLeft"> </td><td class="mdescRight">Cleans cortex-m7 L1 data cache. <br/></td></tr>
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<tr class="separator:gab1dcfc930ee90724a807f69428a1f269"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga49c6ba08328943022264442f6ce2c090"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga49c6ba08328943022264442f6ce2c090"></a>
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static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#ga49c6ba08328943022264442f6ce2c090">L1CACHE_CleanInvalidateDCache</a> (void)</td></tr>
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<tr class="memdesc:ga49c6ba08328943022264442f6ce2c090"><td class="mdescLeft"> </td><td class="mdescRight">Cleans and Invalidates cortex-m7 L1 data cache. <br/></td></tr>
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<tr class="separator:ga49c6ba08328943022264442f6ce2c090"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga9baff800f4d60a09efc4e4ce309dd583"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#ga9baff800f4d60a09efc4e4ce309dd583">L1CACHE_InvalidateDCacheByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:ga9baff800f4d60a09efc4e4ce309dd583"><td class="mdescLeft"> </td><td class="mdescRight">Invalidates cortex-m7 L1 data cache by range. <a href="#ga9baff800f4d60a09efc4e4ce309dd583">More...</a><br/></td></tr>
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<tr class="separator:ga9baff800f4d60a09efc4e4ce309dd583"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gad120776b1a7f2f3f21b2bf017dbab095"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gad120776b1a7f2f3f21b2bf017dbab095">L1CACHE_CleanDCacheByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:gad120776b1a7f2f3f21b2bf017dbab095"><td class="mdescLeft"> </td><td class="mdescRight">Cleans cortex-m7 L1 data cache by range. <a href="#gad120776b1a7f2f3f21b2bf017dbab095">More...</a><br/></td></tr>
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<tr class="separator:gad120776b1a7f2f3f21b2bf017dbab095"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga4837708efaec2927416b268d75412361"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#ga4837708efaec2927416b268d75412361">L1CACHE_CleanInvalidateDCacheByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:ga4837708efaec2927416b268d75412361"><td class="mdescLeft"> </td><td class="mdescRight">Cleans and Invalidates cortex-m7 L1 data cache by range. <a href="#ga4837708efaec2927416b268d75412361">More...</a><br/></td></tr>
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<tr class="separator:ga4837708efaec2927416b268d75412361"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)</h2></td></tr>
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<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp15e7a9b463a20c013988f37a2d8c9ee1"></a>Mainly used for many drivers for easy cache operation. </p>
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</td></tr>
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<tr class="memitem:ga00cdccb5c53201a747f2a3e2009f43cc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#ga00cdccb5c53201a747f2a3e2009f43cc">ICACHE_InvalidateByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:ga00cdccb5c53201a747f2a3e2009f43cc"><td class="mdescLeft"> </td><td class="mdescRight">Invalidates all instruction caches by range. <a href="#ga00cdccb5c53201a747f2a3e2009f43cc">More...</a><br/></td></tr>
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<tr class="separator:ga00cdccb5c53201a747f2a3e2009f43cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gab5c47d7193562d7a763b1bc1bd91b28c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gab5c47d7193562d7a763b1bc1bd91b28c">DCACHE_InvalidateByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:gab5c47d7193562d7a763b1bc1bd91b28c"><td class="mdescLeft"> </td><td class="mdescRight">Invalidates all data caches by range. <a href="#gab5c47d7193562d7a763b1bc1bd91b28c">More...</a><br/></td></tr>
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<tr class="separator:gab5c47d7193562d7a763b1bc1bd91b28c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga893959336987f85910fe98ab9f7f8648"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#ga893959336987f85910fe98ab9f7f8648">DCACHE_CleanByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:ga893959336987f85910fe98ab9f7f8648"><td class="mdescLeft"> </td><td class="mdescRight">Cleans all data caches by range. <a href="#ga893959336987f85910fe98ab9f7f8648">More...</a><br/></td></tr>
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<tr class="separator:ga893959336987f85910fe98ab9f7f8648"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gac20095b525889cf55c105658877c2c84"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00259.html#gac20095b525889cf55c105658877c2c84">DCACHE_CleanInvalidateByRange</a> (uint32_t address, uint32_t size_byte)</td></tr>
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<tr class="memdesc:gac20095b525889cf55c105658877c2c84"><td class="mdescLeft"> </td><td class="mdescRight">Cleans and Invalidates all data caches by range. <a href="#gac20095b525889cf55c105658877c2c84">More...</a><br/></td></tr>
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<tr class="separator:gac20095b525889cf55c105658877c2c84"><td class="memSeparator" colspan="2"> </td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<td class="memname">#define FSL_CACHE_DRIVER_VERSION   (<a class="el" href="a00260.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 0, 4))</td>
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<h2 class="groupheader">Function Documentation</h2>
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<td class="memname">void L1CACHE_InvalidateICacheByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>size_byte</em> </td>
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<td></td>
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<td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The start address of the memory to be invalidated. </td></tr>
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<tr><td class="paramname">size_byte</td><td>The memory size. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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<td class="memname">static void L1CACHE_InvalidateDCacheByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>size_byte</em> </td>
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<td>)</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The start address of the memory to be invalidated. </td></tr>
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<tr><td class="paramname">size_byte</td><td>The memory size. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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<td class="memname">static void L1CACHE_CleanDCacheByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>size_byte</em> </td>
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<td></td>
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The start address of the memory to be cleaned. </td></tr>
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<tr><td class="paramname">size_byte</td><td>The memory size. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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<td class="memname">static void L1CACHE_CleanInvalidateDCacheByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>size_byte</em> </td>
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<td></td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The start address of the memory to be clean and invalidated. </td></tr>
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<tr><td class="paramname">size_byte</td><td>The memory size. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 D-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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<td class="memname">void ICACHE_InvalidateByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<p>Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The physical address. </td></tr>
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<tr><td class="paramname">size_byte</td><td>size of the memory to be invalidated. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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<td class="memname">void DCACHE_InvalidateByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramname"><em>size_byte</em> </td>
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<td></td>
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<p>Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The physical address. </td></tr>
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<tr><td class="paramname">size_byte</td><td>size of the memory to be invalidated. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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<td class="memname">void DCACHE_CleanByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramname"><em>size_byte</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</div><div class="memdoc">
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<p>Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The physical address. </td></tr>
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<tr><td class="paramname">size_byte</td><td>size of the memory to be cleaned. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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<td class="memname">void DCACHE_CleanInvalidateByRange </td>
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<td>(</td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>address</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>size_byte</em> </td>
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</tr>
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<tr>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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</table>
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</div><div class="memdoc">
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<p>Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">address</td><td>The physical address. </td></tr>
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<tr><td class="paramname">size_byte</td><td>size of the memory to be cleaned and invalidated. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section note"><dt>Note</dt><dd>address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned. </dd></dl>
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