344 lines
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344 lines
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 <span id="projectnumber">Rev 2.15.000</span>
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<div id="projectbrief">NXP Semiconductors</div>
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<a href="#func-members">Functions</a> </div>
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<div class="title">GPC: General Power Controller Driver</div> </div>
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</div><!--header-->
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<div class="contents">
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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
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<p>The MCUXpresso SDK provides a peripheral driver for the General Power Controller (GPC) module of MCUXpresso SDK devices.</p>
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<p>API functions are provided to configure the system about working in dedicated power mode. There are mainly about enabling the power for memory, enabling the wakeup sources for STOP modes, and power up/down operations for various peripherals. </p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
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<tr class="memitem:ga7c73d81bfb34ebb7ca40a5ad2a63ad7e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00267.html#ga7c73d81bfb34ebb7ca40a5ad2a63ad7e">GPC_EnableIRQ</a> (GPC_Type *base, uint32_t irqId)</td></tr>
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<tr class="memdesc:ga7c73d81bfb34ebb7ca40a5ad2a63ad7e"><td class="mdescLeft"> </td><td class="mdescRight">Enable the IRQ. <a href="#ga7c73d81bfb34ebb7ca40a5ad2a63ad7e">More...</a><br/></td></tr>
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<tr class="separator:ga7c73d81bfb34ebb7ca40a5ad2a63ad7e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gacfd07601d1a0e90e3b80fffe14830010"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00267.html#gacfd07601d1a0e90e3b80fffe14830010">GPC_DisableIRQ</a> (GPC_Type *base, uint32_t irqId)</td></tr>
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<tr class="memdesc:gacfd07601d1a0e90e3b80fffe14830010"><td class="mdescLeft"> </td><td class="mdescRight">Disable the IRQ. <a href="#gacfd07601d1a0e90e3b80fffe14830010">More...</a><br/></td></tr>
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<tr class="separator:gacfd07601d1a0e90e3b80fffe14830010"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga1118000efd3c822329c63a7155bbe12e"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="a00267.html#ga1118000efd3c822329c63a7155bbe12e">GPC_GetIRQStatusFlag</a> (GPC_Type *base, uint32_t irqId)</td></tr>
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<tr class="memdesc:ga1118000efd3c822329c63a7155bbe12e"><td class="mdescLeft"> </td><td class="mdescRight">Get the IRQ/Event flag. <a href="#ga1118000efd3c822329c63a7155bbe12e">More...</a><br/></td></tr>
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<tr class="separator:ga1118000efd3c822329c63a7155bbe12e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ga8270fba73a065a4e14af1bc895e55969"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00267.html#ga8270fba73a065a4e14af1bc895e55969">GPC_RequestPdram0PowerDown</a> (GPC_Type *base, bool enable)</td></tr>
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<tr class="memdesc:ga8270fba73a065a4e14af1bc895e55969"><td class="mdescLeft"> </td><td class="mdescRight">FLEXRAM PDRAM0 Power Gate Enable. <a href="#ga8270fba73a065a4e14af1bc895e55969">More...</a><br/></td></tr>
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<tr class="separator:ga8270fba73a065a4e14af1bc895e55969"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:gaac50bee55eb34b329680e6fd0d2a9582"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="a00267.html#gaac50bee55eb34b329680e6fd0d2a9582">GPC_RequestMEGAPowerOn</a> (GPC_Type *base, bool enable)</td></tr>
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<tr class="memdesc:gaac50bee55eb34b329680e6fd0d2a9582"><td class="mdescLeft"> </td><td class="mdescRight">Requests the MEGA power switch sequence. <a href="#gaac50bee55eb34b329680e6fd0d2a9582">More...</a><br/></td></tr>
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<tr class="separator:gaac50bee55eb34b329680e6fd0d2a9582"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
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Driver version</h2></td></tr>
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<tr class="memitem:ga91a1b6b08dc09200c3b0ee314b362b74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="a00267.html#ga91a1b6b08dc09200c3b0ee314b362b74">FSL_GPC_DRIVER_VERSION</a>   (<a class="el" href="a00260.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 1, 1))</td></tr>
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<tr class="memdesc:ga91a1b6b08dc09200c3b0ee314b362b74"><td class="mdescLeft"> </td><td class="mdescRight">GPC driver version 2.1.1. <a href="#ga91a1b6b08dc09200c3b0ee314b362b74">More...</a><br/></td></tr>
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<tr class="separator:ga91a1b6b08dc09200c3b0ee314b362b74"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<h2 class="groupheader">Macro Definition Documentation</h2>
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<a class="anchor" id="ga91a1b6b08dc09200c3b0ee314b362b74"></a>
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<td class="memname">#define FSL_GPC_DRIVER_VERSION   (<a class="el" href="a00260.html#ga812138aa3315b0c6953c1a26130bcc37">MAKE_VERSION</a>(2, 1, 1))</td>
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<h2 class="groupheader">Function Documentation</h2>
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<td class="memname">void GPC_EnableIRQ </td>
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<td>(</td>
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<td class="paramtype">GPC_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irqId</em> </td>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>GPC peripheral base address. </td></tr>
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<tr><td class="paramname">irqId</td><td>ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms. </td></tr>
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<td class="memname">void GPC_DisableIRQ </td>
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<td>(</td>
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<td class="paramtype">GPC_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irqId</em> </td>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>GPC peripheral base address. </td></tr>
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<tr><td class="paramname">irqId</td><td>ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms. </td></tr>
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</table>
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</dd>
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</dl>
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<td class="memname">bool GPC_GetIRQStatusFlag </td>
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<td>(</td>
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<td class="paramtype">GPC_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">uint32_t </td>
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<td class="paramname"><em>irqId</em> </td>
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<td></td>
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<td>)</td>
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<td></td><td></td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>GPC peripheral base address. </td></tr>
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<tr><td class="paramname">irqId</td><td>ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms. </td></tr>
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</table>
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</dd>
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</dl>
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<dl class="section return"><dt>Returns</dt><dd>Indicated IRQ/Event is asserted or not. </dd></dl>
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<td class="memname">static void GPC_RequestPdram0PowerDown </td>
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<td>(</td>
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<td class="paramtype">GPC_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramkey"></td>
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<td></td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<td>)</td>
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<td class="mlabels-right">
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<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
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<p>This function configures the FLEXRAM PDRAM0 if it will keep power when cpu core is power down. When the PDRAM0 Power is 1, PDRAM0 will be power down once when CPU core is power down. When the PDRAM0 Power is 0, PDRAM0 will keep power on even if CPU core is power down. When CPU core is re-power up, the default setting is 1.</p>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>GPC peripheral base address. </td></tr>
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<tr><td class="paramname">enable</td><td>Enable the request or not. </td></tr>
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</table>
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</dd>
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<td class="memname">static void GPC_RequestMEGAPowerOn </td>
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<td>(</td>
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<td class="paramtype">GPC_Type * </td>
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<td class="paramname"><em>base</em>, </td>
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<td class="paramtype">bool </td>
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<td class="paramname"><em>enable</em> </td>
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<td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
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<tr><td class="paramname">base</td><td>GPC peripheral base address. </td></tr>
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<tr><td class="paramname">enable</td><td>Enable the power on sequence, or the power down sequence. </td></tr>
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</table>
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</dd>
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</dl>
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<li class="footer">© 2016 NXP Semiconductors. All rights reserved.
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