188 lines
5.9 KiB
C
188 lines
5.9 KiB
C
/*
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* Copyright 2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ISL29023_H_
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#define ISL29023_H_
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/**
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**
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** ISL29023 Ambient Light Sensor Internal Registers
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*/
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enum {
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ISL29023_CMD_I = 0x00,
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ISL29023_CMD_II = 0x01,
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ISL29023_DATA_LSB = 0x02,
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ISL29023_DATA_MSB = 0x03,
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ISL29023_INT_LT_LSB = 0x04,
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ISL29023_INT_LT_MSB = 0x05,
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ISL29023_INT_HT_LSB = 0x06,
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ISL29023_INT_HT_MSB = 0x07,
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ISL29023_TEST = 0x08,
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};
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#define ISL29023_I2C_ADDRESS (0x44) /*ISL29023 I2C Address */
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#define ISL29023_I2C_TEST_VALUE (0x00) /*ISL29023 test register value */
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/*--------------------------------
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** Register: COMMAND-I
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** Enum: ISL29023_CMD_I
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** --
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** Offset : 0x00 - Control & Status bits
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** ------------------------------*/
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typedef union {
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struct {
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uint8_t prst: 2; /* IRQ persist bits. */
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uint8_t flag: 1; /* IRQ flag bit. */
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uint8_t _reserved_ : 2;
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uint8_t op : 3; /* Operation mode bits. */
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} b;
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uint8_t w;
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} ISL29023_CMD_I_t;
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/*
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** COMMAND-I - Bit field mask definitions
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*/
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#define ISL29023_CMD_I_PRST_MASK ((uint8_t) 0x03)
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#define ISL29023_CMD_I_PRST_SHIFT ((uint8_t) 0)
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#define ISL29023_CMD_I_FLAG_MASK ((uint8_t) 0x04)
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#define ISL29023_CMD_I_FLAG_SHIFT ((uint8_t) 2)
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#define ISL29023_CMD_I_OP_MASK ((uint8_t) 0xe0)
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#define ISL29023_CMD_I_OP_SHIFT ((uint8_t) 5)
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/*
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** COMMAND-I - Bit field value definitions
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*/
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#define ISL29023_CMD_I_PRST_1 ((uint8_t) 0x00) /* Number of Integration Samples = 1 */
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#define ISL29023_CMD_I_PRST_4 ((uint8_t) 0x01) /* Number of Integration Samples = 4 */
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#define ISL29023_CMD_I_PRST_8 ((uint8_t) 0x02) /* Number of Integration Samples = 8 */
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#define ISL29023_CMD_I_PRST_16 ((uint8_t) 0x03) /* Number of Integration Samples = 16 */
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#define ISL29023_CMD_I_FLAG_CLEARED ((uint8_t) 0x00) /* IRQ flag is cleared or not triggered yet */
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#define ISL29023_CMD_I_FLAG_TRIGGERED ((uint8_t) 0x04) /* IRQ flag is triggered */
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#define ISL29023_CMD_I_OP_POWER_DOWN ((uint8_t) 0x00) /* Power-down the device (default) */
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#define ISL29023_CMD_I_OP_ALS_ONCE ((uint8_t) 0x20) /* IC measures ALS only once */
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#define ISL29023_CMD_I_OP_IR_ONCE ((uint8_t) 0x40) /* IC meausres IR only once */
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#define ISL29023_CMD_I_OP_ALS_CONT ((uint8_t) 0xA0) /* IC meausres ALS continuously */
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#define ISL29023_CMD_I_OP_IR_CONT ((uint8_t) 0xC0) /* IC meausres IR continuous */
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/*------------------------------*/
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/*--------------------------------
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** Register: COMMAND-II
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** Enum: ISL29023_CMD_II
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** --
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** Offset : 0x01 - Control bits
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** ------------------------------*/
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typedef union {
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struct {
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uint8_t range: 2; /* Full scale range bits */
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uint8_t res : 2; /* ADC resolution bits */
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uint8_t _reserved_ : 4;
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} b;
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uint8_t w;
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} ISL29023_CMD_II_t;
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/*
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** COMMAND-II - Bit field mask definitions
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*/
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#define ISL29023_CMD_II_RANGE_MASK ((uint8_t) 0x03)
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#define ISL29023_CMD_II_RANGE_SHIFT ((uint8_t) 0)
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#define ISL29023_CMD_II_RES_MASK ((uint8_t) 0x0C)
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#define ISL29023_CMD_II_RES_SHIFT ((uint8_t) 2)
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/*
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** COMMAND-II - Bit field value definitions
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*/
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#define ISL29023_CMD_II_RANGE_1 ((uint8_t) 0x00) /* FSR @ALS Sensing = 1.000 */
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#define ISL29023_CMD_II_RANGE_2 ((uint8_t) 0x01) /* FSR @ALS Sensing = 4.000 */
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#define ISL29023_CMD_II_RANGE_3 ((uint8_t) 0x02) /* FSR @ALS Sensing = 16.000 */
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#define ISL29023_CMD_II_RANGE_4 ((uint8_t) 0x03) /* FSR @ALS Sensing = 64.000 */
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#define ISL29023_CMD_II_RES_16 ((uint8_t) 0x00) /* 2^16 ADC resolution */
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#define ISL29023_CMD_II_RES_12 ((uint8_t) 0x04) /* 2^12 ADC resolution */
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#define ISL29023_CMD_II_RES_8 ((uint8_t) 0x08) /* 2^8 ADC resolution */
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#define ISL29023_CMD_II_RES_4 ((uint8_t) 0x0C) /* 2^4 ADC resolution */
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/*------------------------------*/
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/*--------------------------------
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** Register: DATA_LSB
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** Enum: ISL29023_DATA_LSB
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** --
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** Offset : 0x02 - Bits 7-0 of the 16-bit data register.
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** ------------------------------*/
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typedef uint8_t ISL29023_DATA_LSB_t;
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/*--------------------------------
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** Register: DATA_MSB
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** Enum: ISL29023_DATA_MSB
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** --
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** Offset : 0x03 - Bits 15-8 of the 16-bit data register.
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** ------------------------------*/
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typedef uint8_t ISL29023_DATA_MSB_t;
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/*--------------------------------
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** Register: INT_LT_LSB
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** Enum: ISL29023_INT_LT_LSB
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** --
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** Offset : 0x04 - Bits 7-0 of the 16-bit lower IRQ treshold register.
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** ------------------------------*/
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typedef uint8_t ISL29023_INT_LT_LSB_t;
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/*--------------------------------
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** Register: INT_LT_MSB
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** Enum: ISL29023_INT_LT_MSB
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** --
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** Offset : 0x05 - Bits 15-8 of the 16-bit lower IRQ treshold register.
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** ------------------------------*/
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typedef uint8_t ISL29023_INT_LT_MSB_t;
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/*--------------------------------
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** Register: INT_HT_LSB
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** Enum: ISL29023_INT_HT_LSB
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** --
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** Offset : 0x06 - Bits 7-0 of the 16-bit upper IRQ treshold register.
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** ------------------------------*/
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typedef uint8_t ISL29023_INT_HT_LSB_t;
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/*--------------------------------
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** Register: INT_HT_MSB
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** Enum: ISL29023_INT_HT_MSB
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** --
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** Offset : 0x07 - Bits 15-8 of the 16-bit upper IRQ treshold register.
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** ------------------------------*/
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typedef uint8_t ISL29023_INT_HT_MSB_t;
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/*--------------------------------
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** Register: TEST
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** Enum: ISL29023_TEST
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** --
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** Offset : 0x08 - Test register (hold 00h during normal operation).
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** ------------------------------*/
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typedef uint8_t ISL29023_TEST_t;
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#endif /* ISL29023_H_ */
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