279 lines
12 KiB
C
279 lines
12 KiB
C
/*
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* Copyright 2023 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*! File: nmh1000.h
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* @brief The \b nmh1000.h file contains the register definitions for NMH1000 sensor.
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*/
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#ifndef NMH1000_H_
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#define NMH1000_H_
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/**
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**
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** @brief The NMH1000 Sensor Internal Map.
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*/
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enum {
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NMH1000_STATUS = 0x00,
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NMH1000_CONTROL_REG1 = 0x01,
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NMH1000_RESERVED1 = 0x02,
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NMH1000_OUT_M_REG = 0x03,
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NMH1000_USER_ASSERT_THRESH = 0x04,
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NMH1000_USER_CLEAR_THRESH = 0x05,
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NMH1000_ODR = 0x06,
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NMH1000_RESERVED2 = 0x07,
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NMH1000_WHO_AM_I = 0x08,
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NMH1000_I2C_ADDR = 0x09,
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};
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#define NMH1000_WHO_AM_I_VALUE (0x01)
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/*--------------------------------
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** Register: STATUS
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** Enum: NMH1000_STATUS
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** --
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** Offset : 0x0 - Status reporting register
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** ------------------------------*/
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typedef union {
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struct {
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uint8_t out_b : 1; /* Output Buffer indicate a latched state of the VOUT pin after a transition */
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/* from either Asserted to Clear or Clear to Asserted. */
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uint8_t rst_stat : 1; /* Reset Status shall indicate the state-machine reset sequence. */
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uint8_t _reserved_ : 1;
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uint8_t opmode : 1; /* The read-only OPMODE shall indicate the mode of the internal */
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/* state-machine. */
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uint8_t _reserved_1 : 1;
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uint8_t mdr : 1; /* Magnetic Data Ready shall indicate the value in register $03 is available */
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/* for read operation. */
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uint8_t mdo : 1; /* Magnetic Data Overwrite shall indicate the validity of the value in */
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/* register $03. */
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uint8_t output : 1; /* Vout control block state. */
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} b;
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uint8_t w;
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} NMH1000_STATUS_t;
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/*
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** STATUS - Bit field mask definitions
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*/
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#define NMH1000_STATUS_OUT_B_MASK ((uint8_t) 0x01)
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#define NMH1000_STATUS_OUT_B_SHIFT ((uint8_t) 0)
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#define NMH1000_STATUS_RST_STAT_MASK ((uint8_t) 0x02)
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#define NMH1000_STATUS_RST_STAT_SHIFT ((uint8_t) 1)
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#define NMH1000_STATUS_OPMODE_MASK ((uint8_t) 0x08)
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#define NMH1000_STATUS_OPMODE_SHIFT ((uint8_t) 3)
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#define NMH1000_STATUS_MDR_MASK ((uint8_t) 0x20)
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#define NMH1000_STATUS_MDR_SHIFT ((uint8_t) 5)
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#define NMH1000_STATUS_MDO_MASK ((uint8_t) 0x40)
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#define NMH1000_STATUS_MDO_SHIFT ((uint8_t) 6)
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#define NMH1000_STATUS_OUTPUT_MASK ((uint8_t) 0x80)
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#define NMH1000_STATUS_OUTPUT_SHIFT ((uint8_t) 7)
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/*
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** STATUS - Bit field value definitions
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*/
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#define NMH1000_STATUS_OUT_B_CLEARED ((uint8_t) 0x00) /* OUT Cleared on previous cycle. */
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#define NMH1000_STATUS_OUT_B_ASSERTED ((uint8_t) 0x01) /* OUT asserted on previous cycle. */
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#define NMH1000_STATUS_RST_STAT_RST_SEQ_COMPLETED ((uint8_t) 0x00) /* Reset sequence complete and read operation */
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/* performed on register $00. */
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#define NMH1000_STATUS_RST_STAT_RST_SEQ_NOT_COMPLETED ((uint8_t) 0x02) /* Reset sequence not complete. Result of Reset. */
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#define NMH1000_STATUS_OPMODE_STATE_MACHINE_FAULT ((uint8_t) 0x00) /* ndicates VPP < VSTAND and the device in */
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/* Standalone mode indicating a state machine fault, */
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/* since the registers are only accessible in the */
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/* I2C mode. */
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#define NMH1000_STATUS_OPMODE_USER_MODE ((uint8_t) 0x08) /* Indicates VPP >= VSTAND and the device in I2C User */
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/* Mode. */
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#define NMH1000_STATUS_MDR_DATA_AVAILABLE ((uint8_t) 0x00) /* $03 data available. */
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#define NMH1000_STATUS_MDR_DATA_NOT_AVAILABLE ((uint8_t) 0x20) /* $03 data not available. Result of Reset. */
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#define NMH1000_STATUS_MDO_VALIDITY_IN_RANGE ((uint8_t) 0x00) /* Register $03 value is within the range $00 to $1F. */
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#define NMH1000_STATUS_MDO_VALIDITY_OUT_OF_RANGE ((uint8_t) 0x40) /* Register $03 value is >$1F indicating out-of-range */
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/* or fault. Result of Reset. */
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#define NMH1000_STATUS_OUTPUT_VOUT_DRIVEN_TO_VOL ((uint8_t) 0x00) /* The state of VOUT is driven to VOL; Result of */
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/* Reset. */
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#define NMH1000_STATUS_OUTPUT_VOUT_DRIVEN_TO_VOH ((uint8_t) 0x80) /* The state of VOUT is driven to VOH. */
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/*------------------------------*/
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/*--------------------------------
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** Register: CONTROL_REG1
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** Enum: NMH1000_CONTROL_REG1
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** --
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** Offset : 0x01 - Control Register
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** ------------------------------*/
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typedef union {
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struct {
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uint8_t rst : 1; /* Internal device Soft Reset. */
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uint8_t _reserved_ : 1;
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uint8_t one_short : 1; /* It provides control of the state machine to trigger a single sequence of */
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/* Compare to Vout Control, then halt. The bit shall clear upon the sequence */
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/* being completed. */
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uint8_t auto_mode : 1; /* It provides control of the state machine to enter a sequential autonomous */
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/* mode cycling from Sleep to Compare to Vout Control, then back to Sleep, */
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/* etc. The sequence shall be halted when the AUTO is written to 0. */
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uint8_t i2c_dis : 1; /* Control of the operating mode "on-the'fly" after the device has exited POR */
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/* or Soft Reset. This allows the user to force the device into standalone */
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/* mode. */
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uint8_t v_pol : 1; /* Control of the user-defined OUT pin and resultant OUT_B register bit */
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/* assert / clear polarity. */
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} b;
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uint8_t w;
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} NMH1000_CONTROL_REG1_t;
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/*
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** CONTROL_REG1 - Bit field mask definitions
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*/
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#define NMH1000_CONTROL_REG1_RST_MASK ((uint8_t) 0x01)
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#define NMH1000_CONTROL_REG1_RST_SHIFT ((uint8_t) 0)
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#define NMH1000_CONTROL_REG1_ONE_SHORT_MASK ((uint8_t) 0x04)
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#define NMH1000_CONTROL_REG1_ONE_SHORT_SHIFT ((uint8_t) 2)
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#define NMH1000_CONTROL_REG1_AUTO_MODE_MASK ((uint8_t) 0x08)
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#define NMH1000_CONTROL_REG1_AUTO_MODE_SHIFT ((uint8_t) 3)
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#define NMH1000_CONTROL_REG1_I2C_DIS_MASK ((uint8_t) 0x10)
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#define NMH1000_CONTROL_REG1_I2C_DIS_SHIFT ((uint8_t) 4)
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#define NMH1000_CONTROL_REG1_V_POL_MASK ((uint8_t) 0x20)
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#define NMH1000_CONTROL_REG1_V_POL_SHIFT ((uint8_t) 5)
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/*
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** CONTROL_REG1 - Bit field value definitions
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*/
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#define NMH1000_CONTROL_REG1_RST_NO_RESET ((uint8_t) 0x00) /* No reset is forced. */
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#define NMH1000_CONTROL_REG1_RST_RESET ((uint8_t) 0x01) /* Internal device reset is be forced. */
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#define NMH1000_CONTROL_REG1_ONE_SHORT_EN ((uint8_t) 0x04) /* Trigger a One-Shot sequence. */
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#define NMH1000_CONTROL_REG1_AUTO_MODE_HALT ((uint8_t) 0x00) /* Halts or prevents Autonomous mode. */
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#define NMH1000_CONTROL_REG1_AUTO_MODE_START ((uint8_t) 0x08) /* Start the Autonomous mode. */
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#define NMH1000_CONTROL_REG1_I2C_DIS_STANDALONE_MODE ((uint8_t) 0x10) /* force the device into i2c standalone mode. */
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#define NMH1000_CONTROL_REG1_V_POL_ASSERT_VOH_CLR_VOL ((uint8_t) 0x00) /* Assert = VOH, Clear = VOL; Result of Reset */
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#define NMH1000_CONTROL_REG1_V_POL_ASSERT_VOL_CLR_VOH ((uint8_t) 0x20) /* Assert = VOL, Clear = VOH. */
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/*------------------------------*/
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/*--------------------------------
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** Register: RESERVED_REG_1
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** Enum: NMH1000_RESERVED_REG_1
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** --
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** Offset : 0x02
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** ------------------------------*/
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typedef uint8_t NMH1000_RESERVED_REG_1_t;
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/*--------------------------------
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** Register: OUT_M_REG
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** Enum: NMH1000_OUT_M_REG
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** --
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** Offset : 0x03 - Report of Magnetic Field Strength
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** ------------------------------*/
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typedef uint8_t NMH1000_OUT_M_REG_t;
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/*--------------------------------
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** Register: USER_ASSERT_THRESH
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** Enum: NMH1000_USER_ASSERT_THRESH
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** --
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** Offset : 0x04 - User selectable output Assert Threshold value from $01 to $1F;provides the capability for the user to override the fixed threshold controlling the output assert condition.
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** ------------------------------*/
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typedef uint8_t NMH1000_USER_ASSERT_THRESH_t;
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/*--------------------------------
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** Register: USER_CLEAR_THRESH
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** Enum: NMH1000_USER_CLEAR_THRESH
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** --
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** Offset : 0x05 - User selectable output Clear Threshold value from $01 to $1F;provides the capability for the user to override the fixed threshold controlling the output clear condition.
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** ------------------------------*/
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typedef uint8_t NMH1000_USER_CLEAR_THRESH_t;
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/*--------------------------------
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** Register: USER_ODR
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** Enum: NMH1000_USER_ODR
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** --
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** Offset : 0x06 - User Setting of Sample Rate(ODR)
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** ------------------------------*/
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typedef union {
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struct {
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uint8_t odr : 3;
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} b;
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uint8_t w;
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} NMH1000_USER_ODR_t;
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/*
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** USER_ODR - Bit field mask definitions
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*/
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#define NMH1000_USER_ODR_ODR_MASK ((uint8_t) 0x07)
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#define NMH1000_USER_ODR_ODR_SHIFT ((uint8_t) 0)
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/*
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** USER_ODR - Bit field value definitions
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*/
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#define NMH1000_USER_ODR_ODR_LSP ((uint8_t) 0x00) /* Low sample rate selected */
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#define NMH1000_USER_ODR_ODR_5X_LSP ((uint8_t) 0x01) /* 5*Low sample rate selected */
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#define NMH1000_USER_ODR_ODR_MSP ((uint8_t) 0x02) /* Medium sample rate selected */
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#define NMH1000_USER_ODR_ODR_HSP ((uint8_t) 0x04) /* High sample rate selected */
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#define NMH1000_USER_ODR_ODR_5X_HSP ((uint8_t) 0x05) /* 5*High sample rate selected */
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#define NMH1000_USER_ODR_ODR_10X_HSP ((uint8_t) 0x06) /* 10*High sample rate selected */
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#define NMH1000_USER_ODR_ODR_CONFIG_ERR ((uint8_t) 0x07) /* Coniguration error */
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/*------------------------------*/
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/*--------------------------------
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** Register: RESERVED_REG_2
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** Enum: NMH1000_RESERVED_REG_2
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** --
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** Offset : 0x07
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** ------------------------------*/
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typedef uint8_t NMH1000_RESERVED_REG_2_t;
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/*--------------------------------
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** Register: WHO_AM_I
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** Enum: NMH1000_WHO_AM_I
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** --
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** Offset : 0x08 - Device identification register
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** ------------------------------*/
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typedef uint8_t NMH1000_WHO_AM_I_t;
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/*--------------------------------
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** Register: I2C_ADDR
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** Enum: NMH1000_I2C_ADDR
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** --
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** Offset : 0x09 - I2C Address register
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** ------------------------------*/
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#endif /* NMH1000_H_ */
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// RESERVED1 : 0x02
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// RESERVED2 : 0x07
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// ODR : 0x06
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