210 lines
7.5 KiB
C
210 lines
7.5 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_debug_console.h"
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#include "pin_mux.h"
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#include "board.h"
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#include "fsl_pwm.h"
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#include "fsl_cmp.h"
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#include "fsl_xbara.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* The PWM base address */
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#define DEMO_PWM_BASEADDR PWM1
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#define DEMO_PWM_SUBMODULE kPWM_Module_0
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#define DEMO_PWM_FAULT_INPUT_PIN kPWM_Fault_0
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#define DEMO_PWM_CONTROL_SUBMODULE kPWM_Control_Module_0
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#define DEMO_PWM_CHANNEL kPWM_PwmA
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#define DEMO_PWM_DELAY_VAL 0x0FFFU
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#define DEMO_PWM_CHANNEL_LOCATION_ON_BOARD "J17-8"
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#define DEMO_CMP_BASE CMP1
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#define DEMO_CMP_USER_CHANNEL 0U
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#define DEMO_CMP_DAC_CHANNEL 7U
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#define DEMO_CMP_INPUT_PIN_LOCATION_ON_BOARD "J17-7"
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#define DEMO_DEADTIME_VAL 650U
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#define PWM_SRC_CLK_FREQ CLOCK_GetFreq(kCLOCK_IpgClk)
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/* Sets up the PWM signals for a PWM submodule */
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static void PWM_InitPhasePwm(void);
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/* Sets up the PWM fault protection */
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static void PWM_SetupFaultPwm(void);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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static void PWM_InitPhasePwm(void)
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{
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/* Structure of setup PWM */
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pwm_signal_param_t pwmSignal;
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uint16_t deadTimeVal;
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uint32_t pwmSourceClockInHz, pwmFrequencyInHz = 1U;
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pwmSourceClockInHz = PWM_SRC_CLK_FREQ;
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/* Set deadtime count */
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deadTimeVal = ((uint64_t)pwmSourceClockInHz * DEMO_DEADTIME_VAL) / 1000000000U;
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pwmSignal.pwmChannel = DEMO_PWM_CHANNEL;
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pwmSignal.level = kPWM_HighTrue;
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pwmSignal.dutyCyclePercent = 50U; /* 50 percent dutycycle */
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pwmSignal.deadtimeValue = deadTimeVal;
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pwmSignal.faultState = kPWM_PwmFaultState0;
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PWM_SetupPwm(DEMO_PWM_BASEADDR, DEMO_PWM_SUBMODULE, &pwmSignal, 1U, kPWM_SignedCenterAligned, pwmFrequencyInHz,
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pwmSourceClockInHz);
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/* Set the load okay bit for all submodules to load registers from their buffer */
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PWM_SetPwmLdok(DEMO_PWM_BASEADDR, DEMO_PWM_CONTROL_SUBMODULE, true);
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}
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static void PWM_SetupFaultPwm(void)
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{
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/* Structure of the parameters to configure a PWM fault */
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pwm_fault_param_t pwmFaultParam;
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/* Setup Fault config */
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/* No combination path is available */
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pwmFaultParam.enableCombinationalPath = false;
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/* Logic 1 on the fault input pin indicates fault */
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pwmFaultParam.faultLevel = true;
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/*
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* Automatic fault clearing
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* If use Manual fault clearing mode, then the user must clear fault flags
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*/
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pwmFaultParam.faultClearingMode = kPWM_Automatic;
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pwmFaultParam.recoverMode = kPWM_RecoverFullCycle;
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PWM_SetupFaults(DEMO_PWM_BASEADDR, DEMO_PWM_FAULT_INPUT_PIN, &pwmFaultParam);
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DEMO_PWM_BASEADDR->SM[DEMO_PWM_SUBMODULE].DISMAP[DEMO_PWM_SUBMODULE] = 0x00;
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DEMO_PWM_BASEADDR->SM[DEMO_PWM_SUBMODULE].DISMAP[DEMO_PWM_SUBMODULE] |= PWM_DISMAP_DIS0A(1);
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}
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int main(void)
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{
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/* Structure of initialize PWM */
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pwm_config_t pwmConfig;
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pwm_fault_input_filter_param_t pwmFaultInputFilterParam;
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cmp_config_t mCmpConfigStruct;
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cmp_dac_config_t mCmpDacConfigStruct;
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uint8_t ret = 0U;
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uint16_t i = 0U;
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uint32_t pwmVal = 4U;
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BOARD_ConfigMPU();
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BOARD_InitBootPins();
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BOARD_InitBootClocks();
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BOARD_InitDebugConsole();
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/* Set the PWM Fault inputs to CMP1 output pin */
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XBARA_Init(XBARA);
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XBARA_SetSignalsConnection(XBARA, kXBARA1_InputAcmp1Out, kXBARA1_OutputFlexpwm1Fault0);
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/*
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* mCmpConfigStruct.enableCmp = true;
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* mCmpConfigStruct.hysteresisMode = kCMP_HysteresisLevel0;
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* mCmpConfigStruct.enableHighSpeed = false;
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* mCmpConfigStruct.enableInvertOutput = false;
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* mCmpConfigStruct.useUnfilteredOutput = false;
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* mCmpConfigStruct.enablePinOut = false;
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* mCmpConfigStruct.enableTriggerMode = false;
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*/
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CMP_GetDefaultConfig(&mCmpConfigStruct);
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/* Init the CMP comparator. */
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CMP_Init(DEMO_CMP_BASE, &mCmpConfigStruct);
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/* Configure the DAC channel. */
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mCmpDacConfigStruct.referenceVoltageSource = kCMP_VrefSourceVin2; /* VCC. */
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mCmpDacConfigStruct.DACValue = 32U; /* Half voltage of logic high level. */
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CMP_SetDACConfig(DEMO_CMP_BASE, &mCmpDacConfigStruct);
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CMP_SetInputChannels(DEMO_CMP_BASE, DEMO_CMP_USER_CHANNEL, DEMO_CMP_DAC_CHANNEL);
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/*
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* pwmConfig.enableDebugMode = false;
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* pwmConfig.enableWait = false;
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* pwmConfig.reloadSelect = kPWM_LocalReload;
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* pwmConfig.clockSource = kPWM_BusClock;
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* pwmConfig.prescale = kPWM_Prescale_Divide_1;
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* pwmConfig.initializationControl = kPWM_Initialize_LocalSync;
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* pwmConfig.forceTrigger = kPWM_Force_Local;
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* pwmConfig.reloadFrequency = kPWM_LoadEveryOportunity;
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* pwmConfig.reloadLogic = kPWM_ReloadImmediate;
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* pwmConfig.pairOperation = kPWM_Independent;
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*/
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PWM_GetDefaultConfig(&pwmConfig);
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pwmConfig.prescale = kPWM_Prescale_Divide_1;
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/* Use full cycle reload */
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pwmConfig.reloadLogic = kPWM_ReloadPwmFullCycle;
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/* PWM A & PWM B operate as 2 independent channels */
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pwmConfig.pairOperation = kPWM_Independent;
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pwmConfig.enableDebugMode = true;
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/* Initialize submodule 0 */
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ret = PWM_Init(DEMO_PWM_BASEADDR, DEMO_PWM_SUBMODULE, &pwmConfig);
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if (ret != kStatus_Success)
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{
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PRINTF("\r\nPWM INIT FAILED");
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return 1;
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}
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/* Fault filter count */
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pwmFaultInputFilterParam.faultFilterCount = 0x07U;
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/* Fault filter period; value of 0 will bypass the filter */
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pwmFaultInputFilterParam.faultFilterPeriod = 0x14U;
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/* Disable fault glitch stretch */
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pwmFaultInputFilterParam.faultGlitchStretch = false;
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PWM_SetupFaultInputFilter(DEMO_PWM_BASEADDR, &pwmFaultInputFilterParam);
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PWM_InitPhasePwm();
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PWM_SetupFaultPwm();
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PRINTF("\r\n\r\nWelcome to PWM Fault demo");
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PRINTF("\r\nUse oscilloscope to see PWM signal at probe pin: %s", DEMO_PWM_CHANNEL_LOCATION_ON_BOARD);
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PRINTF("\r\nConnect pin %s to high level and ground to see change.", DEMO_CMP_INPUT_PIN_LOCATION_ON_BOARD);
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PWM_StartTimer(DEMO_PWM_BASEADDR, DEMO_PWM_CONTROL_SUBMODULE);
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CMP_Enable(DEMO_CMP_BASE, true);
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while (1)
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{
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/* Time delay for update the duty cycle percentage */
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for (i = 0U; i < DEMO_PWM_DELAY_VAL; i++)
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{
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__NOP();
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}
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pwmVal = pwmVal + 4;
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/* Reset the duty cycle percentage */
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if (pwmVal > 100)
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{
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pwmVal = 4;
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}
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/* Update duty cycles for PWM signals */
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PWM_UpdatePwmDutycycle(DEMO_PWM_BASEADDR, DEMO_PWM_SUBMODULE, DEMO_PWM_CHANNEL, kPWM_SignedCenterAligned,
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pwmVal);
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/* Set the load okay bit for all submodules to load registers from their buffer */
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PWM_SetPwmLdok(DEMO_PWM_BASEADDR, DEMO_PWM_CONTROL_SUBMODULE, true);
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}
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}
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