92 lines
3.3 KiB
C
92 lines
3.3 KiB
C
/*
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* Copyright 2021 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _APP_H_
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#define _APP_H_
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*${macro:start}*/
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#define EXAMPLE_FLEXSPI FLEXSPI
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#define FLASH_SIZE 0x2000 /* 64Mb/KByte */
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#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE
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#define FLASH_PAGE_SIZE 256
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#define EXAMPLE_SECTOR 6
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#define SECTOR_SIZE 0x1000 /* 4K */
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#define EXAMPLE_FLEXSPI_CLOCK kCLOCK_FlexSpi
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#define FLASH_PORT kFLEXSPI_PortA1
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#define EXAMPLE_FLEXSPI_RX_SAMPLE_CLOCK kFLEXSPI_ReadSampleClkLoopbackFromDqsPad
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#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13
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#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1
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#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2
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#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6
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#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4
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#define NOR_CMD_LUT_SEQ_IDX_READID 8
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#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9
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#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10
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#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11
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#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12
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#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5
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#define CUSTOM_LUT_LENGTH 60
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#define FLASH_QUAD_ENABLE 0x40
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#define FLASH_BUSY_STATUS_POL 1
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#define FLASH_BUSY_STATUS_OFFSET 0
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#define FLASH_ERROR_STATUS_MASK 0x0e
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/*
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* If cache is enabled, this example should maintain the cache to make sure
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* CPU core accesses the memory, not cache only.
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*/
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#define CACHE_MAINTAIN 1
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/*${macro:end}*/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*${variable:start}*/
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#if (defined CACHE_MAINTAIN) && (CACHE_MAINTAIN == 1)
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typedef struct _flexspi_cache_status
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{
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volatile bool DCacheEnableFlag;
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volatile bool ICacheEnableFlag;
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} flexspi_cache_status_t;
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#endif
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/*${variable:end}*/
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*${prototype:start}*/
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void BOARD_InitHardware(void);
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static inline void flexspi_clock_init()
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{
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#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
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/* Switch to PLL2 for XIP to avoid hardfault during re-initialize clock. */
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); /* Set PLL2 PFD2 clock 396MHZ. */
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CLOCK_SetMux(kCLOCK_FlexspiMux, 0x2); /* Choose PLL2 PFD2 clock as flexspi source clock. */
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CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 133M. */
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#else
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const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
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CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 24); /* Set PLL3 PFD0 clock 360MHZ. */
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CLOCK_SetMux(kCLOCK_FlexspiMux, 0x3); /* Choose PLL3 PFD0 clock as flexspi source clock. */
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CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); /* flexspi clock 120M. */
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#endif
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}
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/*${prototype:end}*/
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#endif /* _APP_H_ */
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