429 lines
19 KiB
C
429 lines
19 KiB
C
/*
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* Copyright 2018-2020,2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
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*
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* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
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*
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* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
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*
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* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
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*
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* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
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*
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*/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v8.0
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processor: MIMXRT1021xxxxx
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package_id: MIMXRT1021DAG5A
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mcu_data: ksdk2_0
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processor_version: 10.0.0
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board: MIMXRT1020-EVK
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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#include "clock_config.h"
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#include "fsl_iomuxc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
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- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
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- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
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- {id: CLK_1M.outFreq, value: 1 MHz}
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- {id: CLK_24M.outFreq, value: 24 MHz}
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- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
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- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
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- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
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- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
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- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
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- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
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- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
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- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
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- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
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- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
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- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
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- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
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- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
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- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
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- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
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- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
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- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
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- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
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- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
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settings:
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- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
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- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
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- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
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- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
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- {id: CCM.IPG_PODF.scale, value: '4'}
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- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
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- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
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- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
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- {id: CCM.SEMC_PODF.scale, value: '8'}
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- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
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- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
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- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
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- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
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- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
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- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
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- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
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- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
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- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
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- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
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- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
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- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
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- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
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- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
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- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
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- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
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- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
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- {id: CCM_ANALOG.PLL4.denom, value: '50'}
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- {id: CCM_ANALOG.PLL4.div, value: '47'}
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- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
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- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
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- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
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- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
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sources:
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- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
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.numerator = 0, /* 30 bit numerator of fractional loop divider */
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.denominator = 1, /* 30 bit denominator of fractional loop divider */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
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{
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.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
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{
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.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
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.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
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.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
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.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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/* Init RTC OSC clock frequency. */
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CLOCK_SetRtcXtalFreq(32768U);
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/* Enable 1MHz clock output. */
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XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
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/* Use free 1MHz clock output. */
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XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
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/* Set XTAL 24MHz clock frequency. */
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CLOCK_SetXtalFreq(24000000U);
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/* Enable XTAL 24MHz clock source. */
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CLOCK_InitExternalClk(0);
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/* Enable internal RC. */
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CLOCK_InitRcOsc24M();
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/* Switch clock source to external OSC. */
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CLOCK_SwitchOsc(kCLOCK_XtalOsc);
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/* Set Oscillator ready counter value. */
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CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
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/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
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CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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/* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
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/* Waiting for DCDC_STS_DC_OK bit is asserted */
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while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
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{
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}
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/* Set AHB_PODF. */
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CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
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/* Disable IPG clock gate. */
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CLOCK_DisableClock(kCLOCK_Adc1);
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CLOCK_DisableClock(kCLOCK_Adc2);
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CLOCK_DisableClock(kCLOCK_Xbar1);
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CLOCK_DisableClock(kCLOCK_Xbar2);
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/* Set IPG_PODF. */
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CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
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/* Set ARM_PODF. */
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CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
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/* Set PERIPH_CLK2_PODF. */
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CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
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/* Disable PERCLK clock gate. */
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CLOCK_DisableClock(kCLOCK_Gpt1);
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CLOCK_DisableClock(kCLOCK_Gpt1S);
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CLOCK_DisableClock(kCLOCK_Gpt2);
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CLOCK_DisableClock(kCLOCK_Gpt2S);
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CLOCK_DisableClock(kCLOCK_Pit);
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/* Set PERCLK_PODF. */
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CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
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/* Disable USDHC1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Usdhc1);
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/* Set USDHC1_PODF. */
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CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
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/* Set Usdhc1 clock source. */
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CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
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/* Disable USDHC2 clock gate. */
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CLOCK_DisableClock(kCLOCK_Usdhc2);
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/* Set USDHC2_PODF. */
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CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
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/* Set Usdhc2 clock source. */
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CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
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/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
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* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
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#ifndef SKIP_SYSCLK_INIT
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/* Disable Semc clock gate. */
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CLOCK_DisableClock(kCLOCK_Semc);
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/* Set SEMC_PODF. */
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CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
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/* Set Semc alt clock source. */
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CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
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/* Set Semc clock source. */
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CLOCK_SetMux(kCLOCK_SemcMux, 0);
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#endif
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/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
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* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
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#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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/* Disable Flexspi clock gate. */
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CLOCK_DisableClock(kCLOCK_FlexSpi);
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/* Set FLEXSPI_PODF. */
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CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
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/* Set Flexspi clock source. */
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CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
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#endif
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/* Disable LPSPI clock gate. */
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CLOCK_DisableClock(kCLOCK_Lpspi1);
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CLOCK_DisableClock(kCLOCK_Lpspi2);
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CLOCK_DisableClock(kCLOCK_Lpspi3);
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CLOCK_DisableClock(kCLOCK_Lpspi4);
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/* Set LPSPI_PODF. */
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CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
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/* Set Lpspi clock source. */
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CLOCK_SetMux(kCLOCK_LpspiMux, 2);
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/* Disable TRACE clock gate. */
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CLOCK_DisableClock(kCLOCK_Trace);
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/* Set TRACE_PODF. */
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CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
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/* Set Trace clock source. */
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CLOCK_SetMux(kCLOCK_TraceMux, 0);
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/* Disable SAI1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Sai1);
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/* Set SAI1_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
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/* Set SAI1_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
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/* Set Sai1 clock source. */
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CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
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/* Disable SAI2 clock gate. */
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CLOCK_DisableClock(kCLOCK_Sai2);
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/* Set SAI2_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
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/* Set SAI2_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
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/* Set Sai2 clock source. */
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CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
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/* Disable SAI3 clock gate. */
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CLOCK_DisableClock(kCLOCK_Sai3);
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/* Set SAI3_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
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/* Set SAI3_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
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/* Set Sai3 clock source. */
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CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
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/* Disable Lpi2c clock gate. */
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CLOCK_DisableClock(kCLOCK_Lpi2c1);
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CLOCK_DisableClock(kCLOCK_Lpi2c2);
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CLOCK_DisableClock(kCLOCK_Lpi2c3);
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/* Set LPI2C_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
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/* Set Lpi2c clock source. */
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CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
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/* Disable CAN clock gate. */
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CLOCK_DisableClock(kCLOCK_Can1);
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CLOCK_DisableClock(kCLOCK_Can2);
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CLOCK_DisableClock(kCLOCK_Can1S);
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CLOCK_DisableClock(kCLOCK_Can2S);
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/* Set CAN_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_CanDiv, 1);
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/* Set Can clock source. */
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CLOCK_SetMux(kCLOCK_CanMux, 2);
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/* Disable UART clock gate. */
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CLOCK_DisableClock(kCLOCK_Lpuart1);
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CLOCK_DisableClock(kCLOCK_Lpuart2);
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CLOCK_DisableClock(kCLOCK_Lpuart3);
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CLOCK_DisableClock(kCLOCK_Lpuart4);
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CLOCK_DisableClock(kCLOCK_Lpuart5);
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CLOCK_DisableClock(kCLOCK_Lpuart6);
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CLOCK_DisableClock(kCLOCK_Lpuart7);
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CLOCK_DisableClock(kCLOCK_Lpuart8);
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/* Set UART_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_UartDiv, 0);
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/* Set Uart clock source. */
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CLOCK_SetMux(kCLOCK_UartMux, 0);
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/* Disable SPDIF clock gate. */
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CLOCK_DisableClock(kCLOCK_Spdif);
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/* Set SPDIF0_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
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/* Set SPDIF0_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
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/* Set Spdif clock source. */
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CLOCK_SetMux(kCLOCK_SpdifMux, 3);
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/* Disable Flexio1 clock gate. */
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CLOCK_DisableClock(kCLOCK_Flexio1);
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/* Set FLEXIO1_CLK_PRED. */
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CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
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/* Set FLEXIO1_CLK_PODF. */
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CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
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/* Set Flexio1 clock source. */
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CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
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/* Set Pll3 sw clock source. */
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CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
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/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
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* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
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#ifndef SKIP_SYSCLK_INIT
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#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
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#warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
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#endif
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/* Init System PLL. */
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CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
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/* Init System pfd0. */
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CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
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/* Init System pfd1. */
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CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
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/* Init System pfd2. */
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
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/* Init System pfd3. */
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CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
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#endif
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/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
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* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
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* Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
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#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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/* Init Usb1 PLL. */
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CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
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/* Init Usb1 pfd0. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
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/* Init Usb1 pfd1. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
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/* Init Usb1 pfd2. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
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/* Init Usb1 pfd3. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
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/* Disable Usb1 PLL output for USBPHY1. */
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CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
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#endif
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/* DeInit Audio PLL. */
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CLOCK_DeinitAudioPll();
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/* Bypass Audio PLL. */
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CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
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/* Set divider for Audio PLL. */
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CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
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CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
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/* Enable Audio PLL output. */
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CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
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/* Init Enet PLL. */
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CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
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/* Set preperiph clock source. */
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CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
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/* Set periph clock source. */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0);
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/* Set periph clock2 clock source. */
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
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/* Set per clock source. */
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CLOCK_SetMux(kCLOCK_PerclkMux, 0);
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/* Set clock out1 divider. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
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/* Set clock out1 source. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
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/* Set clock out2 divider. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
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/* Set clock out2 source. */
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CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
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/* Set clock out1 drives clock out1. */
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CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
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/* Disable clock out1. */
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CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
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/* Disable clock out2. */
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CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
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/* Set SAI1 MCLK1 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
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/* Set SAI1 MCLK2 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
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/* Set SAI1 MCLK3 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
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/* Set SAI2 MCLK3 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
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/* Set SAI3 MCLK3 clock source. */
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IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
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/* Set MQS configuration. */
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IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
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/* Set ENET Ref clock source. */
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#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
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IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
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#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
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/* Backward compatibility for original bitfield name */
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IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
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#else
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#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
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#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
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/* Set GPT1 High frequency reference clock source. */
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IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
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/* Set GPT2 High frequency reference clock source. */
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IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
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/* Set SystemCoreClock variable. */
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|
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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}
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