138 lines
5.5 KiB
C
138 lines
5.5 KiB
C
/*
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* Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_device_registers.h"
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#include "fsl_debug_console.h"
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#include "clock_config.h"
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#include "board.h"
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#include "usb_device_config.h"
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#include "usb.h"
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#include "usb_device.h"
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#include "fsl_component_serial_port_usb.h"
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#include "usb_phy.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define CONTROLLER_ID kSerialManager_UsbControllerEhci0
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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void USB_DeviceClockInit(void);
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/*******************************************************************************
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* Code
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******************************************************************************/
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/* The function sets the cacheable memory to shareable, this suggestion is referred from chapter 2.2.1 Memory regions,
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* types and attributes in Cortex-M7 Devices, Generic User Guide */
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void BOARD_ConfigUSBMPU()
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{
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/* Disable I cache and D cache */
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SCB_DisableICache();
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SCB_DisableDCache();
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
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* SubRegionDisable, Size)
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* API in core_cm7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
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* disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and
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* Privileged mode.
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* Use MACROS defined in core_cm7.h:
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* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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* 0 x 0 1 Device shareable
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* 0 0 1 0 Normal not shareable Outer and inner write
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* through no write allocate
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* 0 0 1 1 Normal not shareable Outer and inner write
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* back no write allocate
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* 0 1 1 0 Normal shareable Outer and inner write
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* through no write allocate
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* 0 1 1 1 Normal shareable Outer and inner write
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* back no write allocate
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* 1 0 0 0 Normal not shareable outer and inner
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* noncache
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* 1 1 0 0 Normal shareable outer and inner
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* noncache
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* 1 0 1 1 Normal not shareable outer and inner write
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* back write/read acllocate
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* 1 1 1 1 Normal shareable outer and inner write
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* back write/read acllocate
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* 2 x 0 0 Device not shareable
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
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* policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
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* core_cm7.h.
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*/
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MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
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MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
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/* Enable MPU */
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ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
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/* Enable I cache and D cache */
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SCB_EnableDCache();
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SCB_EnableICache();
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}
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void USB_DeviceClockInit(void)
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{
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#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)
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usb_phy_config_struct_t phyConfig = {
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BOARD_USB_PHY_D_CAL,
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BOARD_USB_PHY_TXCAL45DP,
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BOARD_USB_PHY_TXCAL45DM,
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};
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#endif
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#if defined(USB_DEVICE_CONFIG_EHCI) && (USB_DEVICE_CONFIG_EHCI > 0U)
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if (CONTROLLER_ID == kSerialManager_UsbControllerEhci0)
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{
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CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
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CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U);
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}
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else
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{
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CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, 480000000U);
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CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, 480000000U);
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}
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USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, &phyConfig);
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#endif
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}
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/*!
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* @brief Main function
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*/
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int main(void)
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{
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char ch;
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/* Init board hardware. */
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BOARD_ConfigMPU();
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BOARD_ConfigUSBMPU();
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BOARD_InitBootClocks();
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USB_DeviceClockInit();
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DbgConsole_Init((uint8_t)CONTROLLER_ID, (uint32_t)NULL, kSerialPort_UsbCdc, (uint32_t)NULL);
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PRINTF("hello world.\r\n");
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while (1)
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{
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ch = GETCHAR();
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PUTCHAR(ch);
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}
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}
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