455 lines
19 KiB
C
455 lines
19 KiB
C
/*
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* Copyright 2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "specific.h"
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#include "fsl_common.h"
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#include "fsl_clock.h"
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#include "lpm.h"
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#include "fsl_iomuxc.h"
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#include "fsl_debug_console.h"
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/*******************************************************************************
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* Code
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******************************************************************************/
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const clock_arm_pll_config_t armPllConfig = {
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.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_sys_pll_config_t sysPllConfig = {
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.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
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.numerator = 0, /* 30 bit numerator of fractional loop divider */
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.denominator = 1, /* 30 bit denominator of fractional loop divider */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_usb_pll_config_t usbPllConfig = {
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.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_audio_pll_config_t audioPllConfig = {
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.loopDivider = 32, /* PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
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.postDivider = 1, /* Divider after the PLL, should only be 1, 2, 4, 8, 16. */
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.numerator = 77, /* 30 bit numerator of fractional loop divider. */
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.denominator = 100, /* 30 bit denominator of fractional loop divider */
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};
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const clock_video_pll_config_t videoPllConfig = {
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.loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
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.postDivider = 8, /* Divider after PLL */
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.numerator = 0, /* 30 bit numerator of fractional loop divider */
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.denominator = 1, /* 30 bit denominator of fractional loop divider */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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const clock_enet_pll_config_t enetPllConfig = {
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.enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
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.enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
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.loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
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.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
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};
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AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode));
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void SwitchSystemClocks(lpm_power_mode_t power_mode)
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{
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#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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LPM_EnterCritical();
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while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
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{
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}
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FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
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/* Disable clock gate of flexspi. */
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CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK);
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#endif
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switch (power_mode)
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{
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case LPM_PowerModeOverRun:
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CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
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CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
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CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0
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/* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */
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CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1);
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CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
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CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
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CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
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CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL
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CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK
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break;
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case LPM_PowerModeFullRun:
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CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
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CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
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CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0
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/* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */
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CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1);
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CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
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CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
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CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
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CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL
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CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK
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break;
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case LPM_PowerModeLowSpeedRun:
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case LPM_PowerModeSysIdle:
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CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
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CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode
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CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2
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/* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */
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CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
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CLOCK_SET_DIV(kCLOCK_IpgDiv, 3);
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CLOCK_SET_DIV(kCLOCK_AhbDiv, 3);
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CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
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CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // Switch PRE_PERIPH_CLK to SYS PLL
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CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // Switch PERIPH_CLK to PRE_PERIPH_CLK
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break;
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case LPM_PowerModeLowPowerRun:
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case LPM_PowerModeLPIdle:
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CLOCK_SET_DIV(kCLOCK_PeriphClk2Div, 0);
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CLOCK_SET_MUX(kCLOCK_PeriphClk2Mux, 1); // PERIPH_CLK2 mux to OSC
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CLOCK_SET_MUX(kCLOCK_PeriphMux, 1); // PERIPH_CLK mux to PERIPH_CLK2
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CLOCK_SET_DIV(kCLOCK_SemcDiv, 0);
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CLOCK_SET_MUX(kCLOCK_SemcMux, 0); // SEMC mux to PERIPH_CLK
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CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode
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CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre
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/* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */
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CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
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CLOCK_SET_DIV(kCLOCK_IpgDiv, 1);
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CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
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CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
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break;
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default:
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break;
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}
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#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
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/* Enable clock gate of flexspi. */
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CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);
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if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode))
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{
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FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19);
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}
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else
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{
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FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15);
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}
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FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
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FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
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while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
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{
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}
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while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
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{
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}
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LPM_ExitCritical();
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#endif
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}
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void ClockSetToOverDriveRun(void)
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{
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// CORE CLK mux to 24M before reconfigure PLLs
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SwitchSystemClocks(LPM_PowerModeLowPowerRun);
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/* Init ARM PLL */
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CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
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CLOCK_InitArmPll(&armPllConfig);
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/* Init SYS PLL*/
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CLOCK_InitSysPll(&sysPllConfig);
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/* Init System pfd0. */
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CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
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/* Init System pfd1. */
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CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
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/* Init System pfd2. */
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
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/* Init System pfd3. */
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CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
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/* Init USB1 PLL. */
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CLOCK_InitUsb1Pll(&usbPllConfig);
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/* Init Usb1 pfd0. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
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/* Init Usb1 pfd1. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
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/* Init Usb1 pfd2. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
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/* Init Usb1 pfd3. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
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/* Init USB2 PLL*/
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CLOCK_InitUsb2Pll(&usbPllConfig);
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/* Init AUDIO PLL */
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CLOCK_InitAudioPll(&audioPllConfig);
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/* Init VIDEO PLL */
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CLOCK_InitVideoPll(&videoPllConfig);
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/* Init ENET PLL */
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CLOCK_InitEnetPll(&enetPllConfig);
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SwitchSystemClocks(LPM_PowerModeOverRun);
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}
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void ClockSetToFullSpeedRun(void)
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{
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// CORE CLK mux to 24M before reconfigure PLLs
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SwitchSystemClocks(LPM_PowerModeLowPowerRun);
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/* Init ARM PLL */
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CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
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CLOCK_InitArmPll(&armPllConfig);
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/* Init SYS PLL. */
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CLOCK_InitSysPll(&sysPllConfig);
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/* Init System pfd0. */
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CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
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/* Init System pfd1. */
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CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
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/* Init System pfd2. */
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
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/* Init System pfd3. */
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CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
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/* Init USB1 PLL. */
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CLOCK_InitUsb1Pll(&usbPllConfig);
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/* Init Usb1 pfd0. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
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/* Init Usb1 pfd1. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
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/* Init Usb1 pfd2. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
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/* Init Usb1 pfd3. */
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CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
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/* Init USB2 PLL*/
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CLOCK_InitUsb2Pll(&usbPllConfig);
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/* Init AUDIO PLL */
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CLOCK_InitAudioPll(&audioPllConfig);
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/* Init VIDEO PLL */
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CLOCK_InitVideoPll(&videoPllConfig);
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/* Init ENET PLL */
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CLOCK_InitEnetPll(&enetPllConfig);
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SwitchSystemClocks(LPM_PowerModeFullRun);
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}
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void ClockSetToLowSpeedRun(void)
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{
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// CORE CLK mux to 24M before reconfigure PLLs
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SwitchSystemClocks(LPM_PowerModeLowPowerRun);
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/* Deinit ARM PLL */
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CLOCK_DeinitArmPll();
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/* Init SYS PLL */
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CLOCK_InitSysPll(&sysPllConfig);
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/* Deinit SYS PLL PFD 0 1 3 */
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CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
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CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
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/* Init System pfd2. */
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
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CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
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/* Deinit USB1 PLL */
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CLOCK_DeinitUsb1Pll();
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/* Deinit USB1 PLL PFD 0 1 2 3 */
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
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/* Deinit USB2 PLL */
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CLOCK_DeinitUsb2Pll();
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/* Deinit AUDIO PLL */
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CLOCK_DeinitAudioPll();
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/* Deinit VIDEO PLL */
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CLOCK_DeinitVideoPll();
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/* Deinit ENET PLL */
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CLOCK_DeinitEnetPll();
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SwitchSystemClocks(LPM_PowerModeLowSpeedRun);
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}
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void ClockSetToLowPowerRun(void)
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{
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// CORE CLK mux to 24M before reconfigure PLLs
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SwitchSystemClocks(LPM_PowerModeLowPowerRun);
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/* Deinit ARM PLL */
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CLOCK_DeinitArmPll();
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/* Deinit SYS PLL */
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CLOCK_DeinitSysPll();
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/* Deinit SYS PLL PFD 0 1 2 3 */
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CLOCK_DeinitSysPfd(kCLOCK_Pfd0);
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CLOCK_DeinitSysPfd(kCLOCK_Pfd1);
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CLOCK_DeinitSysPfd(kCLOCK_Pfd2);
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CLOCK_DeinitSysPfd(kCLOCK_Pfd3);
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/* Power Down USB1 PLL */
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CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK;
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CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK;
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CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK;
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/* Deinit USB1 PLL PFD 0 1 2 3 */
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0);
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1);
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2);
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CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3);
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/* Deinit USB2 PLL */
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CLOCK_DeinitUsb2Pll();
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/* Deinit AUDIO PLL */
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CLOCK_DeinitAudioPll();
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/* Deinit VIDEO PLL */
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CLOCK_DeinitVideoPll();
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/* Deinit ENET PLL */
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CLOCK_DeinitEnetPll();
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}
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void ConfigUartRxPinToGpio(void)
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{
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2) | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK);
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}
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void ReConfigUartRxPin(void)
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{
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RXD, IOMUXC_SW_PAD_CTL_PAD_SPEED(2));
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}
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#define GPR4_STOP_REQ_BITS \
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(IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK)
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#define GPR4_STOP_ACK_BITS \
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(IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK)
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#define GPR7_STOP_REQ_BITS \
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(IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK | \
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IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK)
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#define GPR7_STOP_ACK_BITS \
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(IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK | \
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IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK)
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#define GPR8_DOZE_BITS \
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(IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK | \
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IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK | \
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IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK | \
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IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK | \
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IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK | \
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IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK | \
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IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK | \
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IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK)
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#define GPR8_STOP_MODE_BITS \
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(IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK | \
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IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK | \
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IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK | \
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IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK | \
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IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK | \
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IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK | \
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IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK | \
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IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK)
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#define GPR12_DOZE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK)
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#define GPR12_STOP_MODE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK)
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void PeripheralEnterDozeMode(void)
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{
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IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS;
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IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS;
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}
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void PeripheralExitDozeMode(void)
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{
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IOMUXC_GPR->GPR8 = 0x00000000;
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IOMUXC_GPR->GPR12 = 0x00000000;
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}
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void PeripheralEnterStopMode(void)
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{
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IOMUXC_GPR->GPR4 = IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK;
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while ((IOMUXC_GPR->GPR4 & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) != IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK)
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{
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}
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IOMUXC_GPR->GPR4 = GPR4_STOP_REQ_BITS;
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IOMUXC_GPR->GPR7 = GPR7_STOP_REQ_BITS;
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IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS | GPR8_STOP_MODE_BITS;
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IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS | GPR12_STOP_MODE_BITS;
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while ((IOMUXC_GPR->GPR4 & GPR4_STOP_ACK_BITS) != GPR4_STOP_ACK_BITS)
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{
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}
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while ((IOMUXC_GPR->GPR7 & GPR7_STOP_ACK_BITS) != GPR7_STOP_ACK_BITS)
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{
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}
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}
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void APP_PrintRunFrequency(int32_t run_freq_only)
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{
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PRINTF("\r\n");
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PRINTF("***********************************************************\r\n");
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PRINTF("CPU: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_CpuClk));
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PRINTF("AHB: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_AhbClk));
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PRINTF("SEMC: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SemcClk));
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PRINTF("IPG: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_IpgClk));
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PRINTF("PER: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_PerClk));
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PRINTF("OSC: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_OscClk));
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PRINTF("RTC: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_RtcClk));
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if (!run_freq_only)
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{
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PRINTF("ARMPLL: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_ArmPllClk));
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PRINTF("USB1PLL: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk));
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PRINTF("USB1PLLPFD0: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk));
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PRINTF("USB1PLLPFD1: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk));
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PRINTF("USB1PLLPFD2: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk));
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PRINTF("USB1PLLPFD3: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk));
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PRINTF("USB2PLL: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk));
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PRINTF("SYSPLL: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllClk));
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PRINTF("SYSPLLPFD0: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk));
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PRINTF("SYSPLLPFD1: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk));
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PRINTF("SYSPLLPFD2: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk));
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PRINTF("SYSPLLPFD3: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk));
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PRINTF("ENETPLL0: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk));
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PRINTF("ENETPLL1: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk));
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PRINTF("AUDIOPLL: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_AudioPllClk));
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PRINTF("VIDEOPLL: %d Hz\r\n", CLOCK_GetFreq(kCLOCK_VideoPllClk));
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}
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PRINTF("***********************************************************\r\n");
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PRINTF("\r\n");
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}
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