118 lines
4.2 KiB
C
118 lines
4.2 KiB
C
/*
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* Copyright 2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_romapi.h"
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#if !defined(XIP_EXTERNAL_FLASH) || (XIP_EXTERNAL_FLASH != 1)
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 6U
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#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 7U
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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static status_t FLEXSPI_NorFlash_HyperBusWrite(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes);
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static status_t FLEXSPI_NorFlash_HyperBusRead(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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static status_t FLEXSPI_NorFlash_HyperBusWrite(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes)
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{
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flexspi_xfer_t xfer;
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xfer.operation = kFLEXSPIOperation_Write;
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xfer.seqId = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA;
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xfer.seqNum = 1U;
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xfer.baseAddress = addr * 2U; // word address for HyperFlash
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xfer.isParallelModeEnable = false;
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xfer.txBuffer = buffer;
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xfer.txSize = bytes;
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status_t status = ROM_FLEXSPI_NorFlash_CommandXfer(instance, &xfer);
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return status;
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}
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static status_t FLEXSPI_NorFlash_HyperBusRead(uint32_t instance, uint32_t addr, uint32_t *buffer, uint32_t bytes)
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{
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flexspi_xfer_t xfer;
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xfer.operation = kFLEXSPIOperation_Read;
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xfer.seqId = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA;
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xfer.seqNum = 1U;
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xfer.baseAddress = addr * 2U; // word address for HyperFlash
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xfer.isParallelModeEnable = false;
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xfer.rxBuffer = buffer;
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xfer.rxSize = bytes;
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status_t status = ROM_FLEXSPI_NorFlash_CommandXfer(instance, &xfer);
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return status;
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}
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/*
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* @brief Read ID-CFI Parameters
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*/
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status_t FLEXSPI_NorFlash_VerifyID(uint32_t instance)
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{
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status_t status = kStatus_InvalidArgument;
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uint32_t lut_seq[4];
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memset(lut_seq, 0, sizeof(lut_seq));
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// Write
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lut_seq[0] = FSL_ROM_FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0x20, RADDR_DDR, FLEXSPI_8PAD, 0x18);
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lut_seq[1] = FSL_ROM_FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, WRITE_DDR, FLEXSPI_8PAD, 0x02);
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ROM_FLEXSPI_NorFlash_UpdateLut(instance, HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA, (const uint32_t *)lut_seq, 1U);
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// Read
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memset(lut_seq, 0, sizeof(lut_seq));
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lut_seq[0] = FSL_ROM_FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18);
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lut_seq[1] = FSL_ROM_FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, READ_DDR, FLEXSPI_8PAD, 0x04);
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ROM_FLEXSPI_NorFlash_UpdateLut(instance, HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA, (const uint32_t *)lut_seq, 1U);
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// CFI Entry
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uint32_t buffer[2];
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uint8_t data[4] = {0x00, 0x98};
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status = FLEXSPI_NorFlash_HyperBusWrite(instance, 0x555U, (uint32_t *)data, 2U);
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if (status != kStatus_Success)
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{
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return status;
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}
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// ID-CFI Read
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// Read Query Unique ASCII String
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status = FLEXSPI_NorFlash_HyperBusRead(instance, 0x10U, &buffer[0], sizeof(buffer));
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if (status != kStatus_Success)
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{
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return status;
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}
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buffer[1] &= 0xFFFF;
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// Check that the data read out is unicode "QRY" in big-endian order
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if ((buffer[0] != 0x52005100U) || (buffer[1] != 0x5900U))
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{
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status = kStatus_ROM_FLEXSPINOR_Flash_NotFound;
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return status;
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}
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// ASO Exit 0xF000
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data[1] = 0xF0U;
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status = FLEXSPI_NorFlash_HyperBusWrite(instance, 0x0U, (uint32_t *)data, 2U);
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if (status != kStatus_Success)
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{
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return status;
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}
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return status;
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}
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#endif // XIP_EXTERNAL_FLASH
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