270 lines
8.6 KiB
C
270 lines
8.6 KiB
C
/*
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* Copyright 2017-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_debug_console.h"
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#include "fsl_device_registers.h"
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#include "pin_mux.h"
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#include "clock_config.h"
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#include "board.h"
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#include "fsl_semc.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define EXAMPLE_SEMC SEMC
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#define EXAMPLE_SEMC_START_ADDRESS (0x80000000U)
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#define EXAMPLE_SEMC_CLK_FREQ CLOCK_GetFreq(kCLOCK_SemcClk)
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#define SEMC_EXAMPLE_DATALEN (0x1000U)
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#define SEMC_EXAMPLE_WRITETIMES (1000U)
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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extern status_t BOARD_InitSEMC(void);
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static void SEMC_SDRAMReadWrite32Bit(void);
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static void SEMC_SDRAMReadWrite16Bit(void);
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static void SEMC_SDRAMReadWrite8Bit(void);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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uint32_t sdram_writeBuffer[SEMC_EXAMPLE_DATALEN];
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uint32_t sdram_readBuffer[SEMC_EXAMPLE_DATALEN];
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t BOARD_InitSEMC(void)
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{
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semc_config_t config;
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semc_sdram_config_t sdramconfig;
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uint32_t clockFrq = EXAMPLE_SEMC_CLK_FREQ;
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/* Initializes the MAC configure structure to zero. */
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memset(&config, 0, sizeof(semc_config_t));
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memset(&sdramconfig, 0, sizeof(semc_sdram_config_t));
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/* Initialize SEMC. */
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SEMC_GetDefaultConfig(&config);
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config.dqsMode = kSEMC_Loopbackdqspad; /* For more accurate timing. */
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SEMC_Init(SEMC, &config);
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/* Configure SDRAM. */
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sdramconfig.csxPinMux = kSEMC_MUXCSX0;
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sdramconfig.address = 0x80000000;
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sdramconfig.memsize_kbytes = 32 * 1024; /* 32MB = 32*1024*1KBytes*/
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sdramconfig.portSize = kSEMC_PortSize16Bit;
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sdramconfig.burstLen = kSEMC_Sdram_BurstLen1;
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sdramconfig.columnAddrBitNum = kSEMC_SdramColunm_9bit;
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sdramconfig.casLatency = kSEMC_LatencyThree;
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sdramconfig.tPrecharge2Act_Ns = 18; /* Trp 18ns */
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sdramconfig.tAct2ReadWrite_Ns = 18; /* Trcd 18ns */
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sdramconfig.tRefreshRecovery_Ns = 67; /* Use the maximum of the (Trfc , Txsr). */
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sdramconfig.tWriteRecovery_Ns = 12; /* 12ns */
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sdramconfig.tCkeOff_Ns =
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42; /* The minimum cycle of SDRAM CLK off state. CKE is off in self refresh at a minimum period tRAS.*/
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sdramconfig.tAct2Prechage_Ns = 42; /* Tras 42ns */
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sdramconfig.tSelfRefRecovery_Ns = 67;
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sdramconfig.tRefresh2Refresh_Ns = 60;
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sdramconfig.tAct2Act_Ns = 60;
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sdramconfig.tPrescalePeriod_Ns = 160 * (1000000000 / clockFrq);
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sdramconfig.refreshPeriod_nsPerRow = 64 * 1000000 / 8192; /* 64ms/8192 */
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sdramconfig.refreshUrgThreshold = sdramconfig.refreshPeriod_nsPerRow;
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sdramconfig.refreshBurstLen = 1;
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return SEMC_ConfigureSDRAM(SEMC, kSEMC_SDRAM_CS0, &sdramconfig, clockFrq);
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}
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#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
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#include "fsl_cache.h"
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#endif
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/*!
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* @brief Main function
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*/
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int main(void)
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{
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/* Hardware initialize. */
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BOARD_ConfigMPU();
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BOARD_InitBootPins();
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BOARD_InitBootClocks();
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CLOCK_InitSysPfd(kCLOCK_Pfd2, 29);
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/* Set semc clock to 163.86 MHz */
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CLOCK_SetMux(kCLOCK_SemcMux, 1);
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CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
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BOARD_InitDebugConsole();
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PRINTF("\r\n SEMC SDRAM Example Start!\r\n");
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if (BOARD_InitSEMC() != kStatus_Success)
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{
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PRINTF("\r\n SEMC SDRAM Init Failed\r\n");
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}
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/* 32Bit data read and write. */
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SEMC_SDRAMReadWrite32Bit();
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/* 16Bit data read and write. */
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SEMC_SDRAMReadWrite16Bit();
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/* 8Bit data read and write. */
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SEMC_SDRAMReadWrite8Bit();
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PRINTF("\r\n SEMC SDRAM Example End.\r\n");
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while (1)
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{
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}
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}
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void SEMC_SDRAMReadWrite32Bit(void)
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{
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uint32_t index;
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uint32_t datalen = SEMC_EXAMPLE_DATALEN;
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uint32_t *sdram = (uint32_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
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bool result = true;
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PRINTF("\r\n SEMC SDRAM Memory 32 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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/* Prepare data and write to SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_writeBuffer[index] = index;
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sdram[index] = sdram_writeBuffer[index];
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}
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PRINTF("\r\n SEMC SDRAM Read 32 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
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DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
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#endif
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/* Read data from the SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_readBuffer[index] = sdram[index];
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}
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PRINTF("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Start!\r\n");
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/* Compare the two buffers. */
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while (datalen--)
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{
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if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
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{
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result = false;
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break;
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}
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}
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if (!result)
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{
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PRINTF("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Failed!\r\n");
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}
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else
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{
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PRINTF("\r\n SEMC SDRAM 32 bit Data Write and Read Compare Succeed!\r\n");
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}
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}
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static void SEMC_SDRAMReadWrite16Bit(void)
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{
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uint32_t index;
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uint32_t datalen = SEMC_EXAMPLE_DATALEN;
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uint16_t *sdram = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
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bool result = true;
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PRINTF("\r\n SEMC SDRAM Memory 16 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
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memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
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/* Prepare data and write to SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_writeBuffer[index] = index % 0xFFFF;
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sdram[index] = sdram_writeBuffer[index];
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}
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PRINTF("\r\n SEMC SDRAM Read 16 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
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DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
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#endif
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/* Read data from the SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_readBuffer[index] = sdram[index];
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}
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PRINTF("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Start!\r\n");
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/* Compare the two buffers. */
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while (datalen--)
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{
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if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
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{
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result = false;
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break;
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}
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}
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if (!result)
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{
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PRINTF("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Failed!\r\n");
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}
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else
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{
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PRINTF("\r\n SEMC SDRAM 16 bit Data Write and Read Compare Succeed!\r\n");
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}
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}
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static void SEMC_SDRAMReadWrite8Bit(void)
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{
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uint32_t index;
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uint32_t datalen = SEMC_EXAMPLE_DATALEN;
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uint8_t *sdram = (uint8_t *)EXAMPLE_SEMC_START_ADDRESS; /* SDRAM start address. */
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bool result = true;
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PRINTF("\r\n SEMC SDRAM Memory 8 bit Write Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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memset(sdram_writeBuffer, 0, sizeof(sdram_writeBuffer));
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memset(sdram_readBuffer, 0, sizeof(sdram_readBuffer));
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/* Prepare data and write to SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_writeBuffer[index] = index % 0x100;
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sdram[index] = sdram_writeBuffer[index];
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}
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PRINTF("\r\n SEMC SDRAM Read 8 bit Data Start, Start Address 0x%x, Data Length %d !\r\n", sdram, datalen);
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#if defined(CACHE_MAINTAIN) && CACHE_MAINTAIN
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DCACHE_InvalidateByRange(EXAMPLE_SEMC_START_ADDRESS, 4U * SEMC_EXAMPLE_DATALEN);
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#endif
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/* Read data from the SDRAM. */
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for (index = 0; index < datalen; index++)
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{
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sdram_readBuffer[index] = sdram[index];
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}
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PRINTF("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Start!\r\n");
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/* Compare the two buffers. */
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while (datalen--)
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{
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if (sdram_writeBuffer[datalen] != sdram_readBuffer[datalen])
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{
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result = false;
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break;
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}
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}
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if (!result)
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{
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PRINTF("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Failed!\r\n");
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}
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else
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{
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PRINTF("\r\n SEMC SDRAM 8 bit Data Write and Read Compare Succeed!\r\n");
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}
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}
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