509 lines
22 KiB
C
509 lines
22 KiB
C
/*
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* Copyright 2019 NXP
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_common.h"
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#include "fsl_component_exception_handling.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Firstly check the current LR value, All a valid LR EXC_RETURN values have bits[31:5] set to one.
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* If the bits[31:5] of LR is one, then use check the LR to get faulted SP.
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* If bits[31:5] is not all one, then LR have been pushed to current MSP, will loop check MSP to get
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* valid LR value, and use the LR value to get which SP happen faulted.
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* Then check bit[2] of LR to get which SP faulted happen, if bit[2] of LR is one, then fault happen
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* with PSP, if bit[2] of LR is zero, then fault happen with MSP. */
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#if defined(__IAR_SYSTEMS_ICC__) || defined(__GNUC__)
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#define COPY_TO_STACK() \
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__asm volatile("push {r0-r1}"); \
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__asm volatile("push {r0-r5}"); \
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__asm volatile("mrs r1, msp"); \
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__asm volatile("adds r1, r1, #32"); \
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__asm volatile("mov r5, r1"); \
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__asm volatile("and r2, lr,#0xffffffe0"); \
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__asm volatile("cmp r2, #0xffffffe0"); \
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__asm volatile( \
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"beq _lr_case \n" \
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"_loop_check: \n" \
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"mov r4, #4\n" \
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"adds r1, r1, #4\n" \
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"ldr r3,[r1]\n" \
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"and r2, r3,#0xffffffe0 \n" \
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"cmp r2, #0xffffffe0 \n" \
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"bne _loop_check \n" \
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"b _handle_lr\n" \
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"_lr_case: \n" \
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"mov r4, #0\n" \
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"mov r3, lr\n" \
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"_handle_lr: "); \
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__asm volatile("adds r1, r1, r4"); \
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__asm volatile("msr msp, r1"); \
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__asm volatile("tst r3,#4"); \
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__asm volatile( \
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"ite eq \n" \
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"mrseq r0, msp \n" \
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"mrsne r0, psp"); \
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__asm volatile("push {r0}"); \
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__asm volatile("mrs r0, ipsr"); \
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__asm volatile("push {r0}"); \
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__asm volatile("ldr r0, =g_exceptionStackStruct"); \
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__asm volatile("str sp, [r0]"); \
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__asm volatile("sub r5, r5, #32"); \
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__asm volatile("msr msp, r5"); \
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__asm volatile("pop {r0-r5}");
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#elif defined(__ARMCC_VERSION)
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__ASM void COPY_TO_STACK(void)
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{
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PRESERVE8
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EXTERN g_exceptionStackStruct
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push {r0-r1}
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push {r0-r5}
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mrs r1, msp
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adds r1, r1, #32
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mov r5, r1
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and r2, lr, #0xffffffe0
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cmp r2, #0xffffffe0
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beq _lr_case
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_loop_check
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mov r4, #4
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adds r1, r1, #4
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ldr r3, [r1]
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and r2, r3, #0xffffffe0
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cmp r2, #0xffffffe0
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bne _loop_check
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b _handle_lr
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_lr_case
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mov r4, #0
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mov r3, lr
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_handle_lr
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adds r1, r1, r4
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msr msp, r1
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tst r3, #4
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ite eq
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mrseq r0, msp
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mrsne r0, psp
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push{r0}
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mrs r0, ipsr
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push{r0}
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ldr r0, = g_exceptionStackStruct
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str sp,[r0]
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sub r5, r5, #32
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msr msp, r5
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pop {r0-r5}
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bx lr
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ALIGN
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}
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#ifndef __ARMCC_VERSION
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static
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#endif
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exception_stack_data_t *g_exceptionStackStruct = NULL;
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static const scb_data_text_t scb_data_text[] = {{32, 0x000, "CPUID - CPUID Base Register"},
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{32, 0x004, "ICSR - Interrupt Control and State Register"},
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{32, 0x008, "VTOR - Vector Table Offset Register"},
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{32, 0x00C, "AIRCR - Application Interrupt and Reset Control Register"},
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{32, 0x010, "SCR - System Control Register"},
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{32, 0x014, "CCR - Configuration Control Register"},
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{8, 0x018, "SHPR[0] - System Handlers Priority Registers 0"},
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{8, 0x019, "SHPR[1] - System Handlers Priority Registers 1"},
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{8, 0x01a, "SHPR[2] - System Handlers Priority Registers 2"},
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{8, 0x01b, "SHPR[3] - System Handlers Priority Registers 3"},
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{8, 0x01C, "SHPR[4] - System Handlers Priority Registers 4"},
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{8, 0x01d, "SHPR[5] - System Handlers Priority Registers 5"},
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{8, 0x01e, "SHPR[6] - System Handlers Priority Registers 6"},
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{8, 0x01f, "SHPR[7] - System Handlers Priority Registers 7"},
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{8, 0x020, "SHPR[8] - System Handlers Priority Registers 8"},
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{8, 0x021, "SHPR[9] - System Handlers Priority Registers 9"},
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{8, 0x022, "SHPR[10] - System Handlers Priority Registers 10"},
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{8, 0x023, "SHPR[11] - System Handlers Priority Registers 11"},
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{32, 0x024, "SHCSR - System Handler Control and State Register"},
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{32, 0x028, "CFSR - Configurable Fault Status Register"},
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{32, 0x02C, "HFSR - HardFault Status Register"},
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{32, 0x030, "DFSR - Debug Fault Status Register"},
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{32, 0x034, "MMFAR - MemManage Fault Address Register"},
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{32, 0x038, "BFAR - BusFault Address Register"},
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{32, 0x03C, "AFSR - Auxiliary Fault Status Register"},
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{32, 0x040, "ID_PFR[0] - Processor Feature Register"},
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{32, 0x044, "ID_PFR[1] - Processor Feature Register"},
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{32, 0x048, "ID_DFR - Debug Feature Register"},
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{32, 0x04C, "ID_AFR - Auxiliary Feature Register"},
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{32, 0x050, "ID_MFR[0] - Memory Model Feature Register"},
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{32, 0x054, "ID_MFR[1] - Memory Model Feature Register"},
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{32, 0x058, "ID_MFR[2] - Memory Model Feature Register"},
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{32, 0x05C, "ID_MFR[3] - Memory Model Feature Register"},
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{32, 0x060, "ID_ISAR[0] - Instruction Set Attributes Register"},
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{32, 0x064, "ID_ISAR[1] - Instruction Set Attributes Register"},
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{32, 0x068, "ID_ISAR[2] - Instruction Set Attributes Register"},
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{32, 0x06C, "ID_ISAR[3] - Instruction Set Attributes Register"},
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{32, 0x070, "ID_ISAR[4] - Instruction Set Attributes Register"},
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{32, 0x078, "CLIDR - Cache Level ID register"},
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{32, 0x07C, "CTR - Cache Type register"},
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{32, 0x080, "CCSIDR - Cache Size ID Register"},
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{32, 0x084, "CSSELR - Cache Size Selection Register"},
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{32, 0x088, "CPACR - Coprocessor Access Control Register"},
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{32, 0x240, "MVFR0 - Media and VFP Feature Register 0"},
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{32, 0x244, "MVFR1 - Media and VFP Feature Register 1"},
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{32, 0x248, "MVFR2 - Media and VFP Feature Register 2"},
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{32, 0x290, "ITCMCR - Instruction Tightly-Coupled Memory Control Register"},
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{32, 0x294, "DTCMCR - Data Tightly-Coupled Memory Control Registers"},
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{32, 0x298, "AHBPCR - AHBP Control Register"},
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{32, 0x29C, "CACR - L1 Cache Control Register"},
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{32, 0x2A0, "AHBSCR - AHB Slave Control Register"},
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{32, 0x2A8, "ABFSR - Auxiliary Bus Fault Status Register"}};
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if (defined(EXCEPTION_HANDLING_LOG_ENABLE) && (EXCEPTION_HANDLING_LOG_ENABLE == 1U))
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static void EXCEPTION_ConfigurableFaultStatusRegisterPrint(void)
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{
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uint32_t cfsr = SCB->CFSR;
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/* Configurable Fault Status Register */
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(void)EXCEPTION_PRINTF("0x%08X - CFSR - Configurable Fault Status Register\r\n", cfsr);
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/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
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if (0U != (cfsr & SCB_CFSR_IACCVIOL_Msk)) /* SCB CFSR (MMFSR): IACCVIOL Mask */
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{
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(void)EXCEPTION_PRINTF(
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" > The processor attempted an instruction fetch from a location that does not permit execution\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_DACCVIOL_Msk)) /* SCB CFSR (MMFSR): DACCVIOL Mask */
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{
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(void)EXCEPTION_PRINTF(
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" > The processor attempted a load or store at a location that does not permit the operation\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_MSTKERR_Msk)) /* SCB CFSR (MMFSR): MSTKERR Mask */
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{
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(void)EXCEPTION_PRINTF(" > Unstack for an exception return has caused one or more access violations\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_MUNSTKERR_Msk)) /* SCB CFSR (MMFSR): MUNSTKERR Mask */
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{
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(void)EXCEPTION_PRINTF(" > Stacking for an exception entry has caused one or more access violations\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_MLSPERR_Msk)) /* SCB CFSR (MMFSR): MLSPERR Mask */
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{
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(void)EXCEPTION_PRINTF(" > A MemManage fault occurred during floating-point lazy state preservation\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_MMARVALID_Msk)) /* SCB CFSR (MMFSR): MMARVALID Mask */
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{
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(void)EXCEPTION_PRINTF(" > MMAR holds a valid fault address: ");
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(void)EXCEPTION_PRINTF("0x%08X - MMFAR - MemManage Fault Address Register\r\n", SCB->MMFAR);
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}
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/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
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if (0U != (cfsr & SCB_CFSR_IBUSERR_Msk)) /* SCB CFSR (BFSR): IBUSERR Mask */
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{
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(void)EXCEPTION_PRINTF(" > Instruction bus error\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_PRECISERR_Msk)) /* SCB CFSR (BFSR): PRECISERR Mask */
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{
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(void)EXCEPTION_PRINTF(
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" > A data bus error has occurred, PC value stacked for the exception return points to the instruction "
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"that caused the fault\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_IMPRECISERR_Msk)) /* SCB CFSR (BFSR): IMPRECISERR Mask */
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{
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(void)EXCEPTION_PRINTF(
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" > A data bus error has occurred, return address in the stack frame is not related to the instruction "
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"that caused the error\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_UNSTKERR_Msk)) /* SCB CFSR (BFSR): UNSTKERR Mask */
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{
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(void)EXCEPTION_PRINTF(" > Unstack for an exception return has caused one or more BusFaults\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_STKERR_Msk)) /* SCB CFSR (BFSR): STKERR Mask */
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{
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(void)EXCEPTION_PRINTF(" > Stacking for an exception entry has caused one or more BusFaults\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_LSPERR_Msk)) /* SCB CFSR (BFSR): LSPERR Mask */
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{
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(void)EXCEPTION_PRINTF(" > A bus fault occurred during floating-point lazy state preservation\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_BFARVALID_Msk)) /* SCB CFSR (BFSR): BFARVALID Mask */
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{
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(void)EXCEPTION_PRINTF(" > BFAR holds a valid fault address: ");
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(void)EXCEPTION_PRINTF("0x%08X - BFAR - BusFault Address Register\r\n", SCB->BFAR);
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}
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/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
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if (0U != (cfsr & SCB_CFSR_UNDEFINSTR_Msk)) /* SCB CFSR (UFSR): UNDEFINSTR Mask */
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{
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(void)EXCEPTION_PRINTF(" > The processor has attempted to execute an undefined instruction\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_INVSTATE_Msk)) /* SCB CFSR (UFSR): INVSTATE Mask */
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{
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(void)EXCEPTION_PRINTF(
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" > The processor has attempted to execute an instruction that makes illegal use of the EPSR\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_INVPC_Msk)) /* SCB CFSR (UFSR): INVPC Mask */
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{
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(void)EXCEPTION_PRINTF(" > The processor has attempted an illegal load of EXC_RETURN to the PC\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_NOCP_Msk)) /* SCB CFSR (UFSR): NOCP Mask */
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{
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(void)EXCEPTION_PRINTF(" > The processor has attempted to access a coprocessor\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_UNALIGNED_Msk)) /* SCB CFSR (UFSR): UNALIGNED Mask */
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{
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(void)EXCEPTION_PRINTF(" > The processor has made an unaligned memory access\r\n");
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}
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if (0U != (cfsr & SCB_CFSR_DIVBYZERO_Msk)) /* SCB CFSR (UFSR): DIVBYZERO Mask */
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{
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(void)EXCEPTION_PRINTF(" > The processor has executed an SDIV or UDIV instruction with a divisor of 0\r\n");
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}
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}
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static void EXCEPTION_HardFaultStatusRegisterPrint(void)
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{
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uint32_t hfsr = SCB->HFSR;
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/* HardFault Status Register */
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(void)EXCEPTION_PRINTF("0x%08X - HFSR - HardFault Status Register\r\n", hfsr);
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/* SCB Hard Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
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if (0U != (hfsr & SCB_HFSR_VECTTBL_Msk)) /* SCB HFSR: VECTTBL Mask */
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{
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(void)EXCEPTION_PRINTF(" > BusFault on vector table read\r\n");
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}
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if (0U != (hfsr & SCB_HFSR_FORCED_Msk)) /* SCB HFSR: FORCED Mask */
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{
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(void)EXCEPTION_PRINTF(" > Forced HardFault\r\n");
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}
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if (0U != (hfsr & SCB_HFSR_DEBUGEVT_Msk)) /* SCB HFSR: DEBUGEVT Mask */
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{
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(void)EXCEPTION_PRINTF(
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" > Reserved for Debug use. When writing to the register you must write 1 to this bit, otherwise behavior "
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"is unpredictable\r\n");
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}
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}
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static void EXCEPTION_HardFaultRegisterPrint(void)
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{
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(void)EXCEPTION_ConfigurableFaultStatusRegisterPrint();
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(void)EXCEPTION_HardFaultStatusRegisterPrint();
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for (uint32_t i = 0; i < ARRAY_SIZE(scb_data_text); i++)
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{
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if (32U == scb_data_text[i].type)
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{
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(void)EXCEPTION_PRINTF("0x%08X - %s\r\n", *(uint32_t *)(SCB_BASE + scb_data_text[i].offset),
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scb_data_text[i].str);
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}
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else if (8U == scb_data_text[i].type)
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{
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(void)EXCEPTION_PRINTF("0x%08X - %s\r\n", *(uint8_t *)(SCB_BASE + scb_data_text[i].offset), scb_data_text[i].str);
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}
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else
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{
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/* MISRA C-2012 Rule 15.7 */
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}
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}
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}
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#endif
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static void EXCEPTION_StackFramePrint(void)
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{
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#if (defined(EXCEPTION_HANDLING_LOG_ENABLE) && (EXCEPTION_HANDLING_LOG_ENABLE == 1U))
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(void)EXCEPTION_PRINTF("\r\n--- Stack frame -------------------------------------------------------\r\n");
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(void)EXCEPTION_PRINTF(" IPSR= 0x%08X >>>>> ", g_exceptionStackStruct->IPSR);
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switch (g_exceptionStackStruct->IPSR & 0xFFU)
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{
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case 0:
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(void)EXCEPTION_PRINTF("Thread mode");
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break;
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case 1:
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(void)EXCEPTION_PRINTF("Reserved 1");
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break;
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case 2:
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(void)EXCEPTION_PRINTF("NMI");
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break;
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case 3:
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(void)EXCEPTION_PRINTF("HardFault");
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break;
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case 4:
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(void)EXCEPTION_PRINTF("MemManage");
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break;
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case 5:
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(void)EXCEPTION_PRINTF("BusFault");
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break;
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case 6:
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(void)EXCEPTION_PRINTF("UsageFault");
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break;
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case 7:
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(void)EXCEPTION_PRINTF("Reserved 7");
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break;
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case 8:
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(void)EXCEPTION_PRINTF("Reserved 8");
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break;
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case 9:
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(void)EXCEPTION_PRINTF("Reserved 9");
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break;
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case 10:
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(void)EXCEPTION_PRINTF("Reserved 10");
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break;
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case 11:
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(void)EXCEPTION_PRINTF("SVCall");
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break;
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case 12:
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(void)EXCEPTION_PRINTF("Reserved for Debug");
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break;
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case 13:
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(void)EXCEPTION_PRINTF("Reserved 13");
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break;
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case 14:
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(void)EXCEPTION_PRINTF("PendSV");
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break;
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case 15:
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(void)EXCEPTION_PRINTF("SysTick");
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break;
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default:
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(void)EXCEPTION_PRINTF("IRQ%d", (g_exceptionStackStruct->IPSR & 0xFFU) - 16U);
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break;
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}
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(void)EXCEPTION_PRINTF(" <<<<<\r\n");
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(void)EXCEPTION_PRINTF(" R0 = 0x%08X ", g_exceptionStackStruct->R0);
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(void)EXCEPTION_PRINTF(" R1 = 0x%08X ", g_exceptionStackStruct->R1);
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(void)EXCEPTION_PRINTF(" R2 = 0x%08X ", g_exceptionStackStruct->R2);
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(void)EXCEPTION_PRINTF(" R3 = 0x%08X\r\n", g_exceptionStackStruct->R3);
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(void)EXCEPTION_PRINTF(" R12 = 0x%08X ", g_exceptionStackStruct->R12);
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(void)EXCEPTION_PRINTF(" LR = 0x%08X ", g_exceptionStackStruct->LR);
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(void)EXCEPTION_PRINTF(" PC = 0x%08X ", g_exceptionStackStruct->PC);
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(void)EXCEPTION_PRINTF(" PSR = 0x%08X\r\n", g_exceptionStackStruct->xPSR);
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(void)EXCEPTION_PRINTF(" SP (when faulted) = 0x%08X\r\n", g_exceptionStackStruct->SP);
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(void)EXCEPTION_PRINTF("\n--- System Control Block (SCB) ----------------------------------------\r\n");
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(void)EXCEPTION_HardFaultRegisterPrint();
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while (0U != (g_exceptionStackStruct->IPSR & 0xFFU))
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{
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}
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#endif
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}
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static void EXCEPTION_CopyToStack(void)
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{
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/* Push SP (when faulted) and IPSR to MSP and save MSP contain the exception Stack Struct to
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* g_exceptionStackStruct*/
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COPY_TO_STACK();
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}
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void NMI_Handler(void);
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void NMI_Handler(void)
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#if (defined(EXCEPTION_HANDLING_LOG_ENABLE) && (EXCEPTION_HANDLING_LOG_ENABLE == 1U))
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{
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EXCEPTION_DataPrint();
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}
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#else
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{
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while (1)
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{
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}
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}
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#endif
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#if (defined(__MCUXPRESSO) && defined(__SEMIHOST_HARDFAULT_DISABLE)) || (!defined(__MCUXPRESSO))
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void HardFault_Handler(void);
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void HardFault_Handler(void)
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#if (defined(EXCEPTION_HANDLING_LOG_ENABLE) && (EXCEPTION_HANDLING_LOG_ENABLE == 1U))
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{
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EXCEPTION_DataPrint();
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}
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#else
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{
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while (1)
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{
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}
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}
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#endif
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#endif
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void MemManage_Handler(void);
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void MemManage_Handler(void)
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#if (defined(EXCEPTION_HANDLING_LOG_ENABLE) && (EXCEPTION_HANDLING_LOG_ENABLE == 1U))
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{
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EXCEPTION_DataPrint();
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|
}
|
|
#else
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{
|
|
while (1)
|
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{
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}
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}
|
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#endif
|
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void BusFault_Handler(void);
|
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void BusFault_Handler(void)
|
|
#if (defined(EXCEPTION_HANDLING_LOG_ENABLE) && (EXCEPTION_HANDLING_LOG_ENABLE == 1U))
|
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{
|
|
EXCEPTION_DataPrint();
|
|
}
|
|
#else
|
|
{
|
|
while (1)
|
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{
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}
|
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}
|
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#endif
|
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void UsageFault_Handler(void);
|
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void UsageFault_Handler(void)
|
|
#if (defined(EXCEPTION_HANDLING_LOG_ENABLE) && (EXCEPTION_HANDLING_LOG_ENABLE == 1U))
|
|
{
|
|
EXCEPTION_DataPrint();
|
|
}
|
|
#else
|
|
{
|
|
while (1)
|
|
{
|
|
}
|
|
}
|
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#endif
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/*!
|
|
* @brief Exception data print function.
|
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*
|
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* This function should be called at first place in the ISR where the R0-R3, R12, LR, PC and xPSR
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* have been saved in the stack by ARM,
|
|
* so that the SP and IPSR could be saved right after them. By default, exception handling module will
|
|
* overwrite the following ISR as the reference:
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* NMI_Handler, HardFault_Handler, MemManage_Handler, BusFault_Handler, UsageFault_Handler.
|
|
* The users can refer to these ISRs to have their owner ISRs to output the stack frame information.
|
|
*
|
|
* At last, all the stack frame information would be output from UART instance initialized in the debug
|
|
* console if EXCEPTION_HANDLING_LOG_ENABLE is set to 1.
|
|
* USB CDC could not be supported.
|
|
* SWO is not supported yet.
|
|
* If no UART instance is initialized because debug console is not enabled or there is no HW UART instance available,
|
|
* the users need to route EXCEPTION_PRINTF to an available IO function to output the stack frame information.
|
|
* This function should NOT be called in the task context.
|
|
*
|
|
* @note For MCUXpresso IDE, make sure unselect Include semihost Hardfault handler feature on SDK import wizard,
|
|
* otherwise HardFault_Handler function of semihost_hardfault.c project will be used on MCUXpresso project.
|
|
* Make sure __SEMIHOST_HARDFAULT_DISABLE Macro is defined in if want to use HardFault_Handler function
|
|
* in exception_handling.c.
|
|
*
|
|
* @retval No return vaule.
|
|
*/
|
|
|
|
void EXCEPTION_DataPrint(void)
|
|
{
|
|
/* Here set g_exceptionStackStruct to 0x1 to avoid compiler optimization on some compiler */
|
|
g_exceptionStackStruct = (exception_stack_data_t *)0x1;
|
|
(void)EXCEPTION_CopyToStack();
|
|
(void)EXCEPTION_StackFramePrint();
|
|
}
|