781 lines
19 KiB
C
781 lines
19 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_FXOS_H_
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#define _FSL_FXOS_H_
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#include "fsl_common.h"
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#define FXOS8700CQ_ACCEL_RESOLUTION_BITS 14
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/*
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* STATUS Register
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*/
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#define STATUS_00_REG 0x00
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#define ZYXOW_MASK 0x80
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#define ZOW_MASK 0x40
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#define YOW_MASK 0x20
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#define XOW_MASK 0x10
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#define ZYXDR_MASK 0x08
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#define ZDR_MASK 0x04
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#define YDR_MASK 0x02
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#define XDR_MASK 0x01
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/*
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* F_STATUS FIFO Status Register
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*/
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#define F_STATUS_REG 0x00
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#define F_OVF_MASK 0x80
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#define F_WMRK_FLAG_MASK 0x40
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#define F_CNT5_MASK 0x20
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#define F_CNT4_MASK 0x10
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#define F_CNT3_MASK 0x08
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#define F_CNT2_MASK 0x04
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#define F_CNT1_MASK 0x02
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#define F_CNT0_MASK 0x01
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#define F_CNT_MASK 0x3F
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/*
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* XYZ Data Registers
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*/
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#define OUT_X_MSB_REG 0x01
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#define OUT_X_LSB_REG 0x02
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#define OUT_Y_MSB_REG 0x03
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#define OUT_Y_LSB_REG 0x04
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#define OUT_Z_MSB_REG 0x05
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#define OUT_Z_LSB_REG 0x06
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/*
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* F_SETUP FIFO Setup Register
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*/
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#define F_SETUP_REG 0x09
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#define F_MODE1_MASK 0x80
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#define F_MODE0_MASK 0x40
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#define F_WMRK5_MASK 0x20
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#define F_WMRK4_MASK 0x10
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#define F_WMRK3_MASK 0x08
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#define F_WMRK2_MASK 0x04
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#define F_WMRK1_MASK 0x02
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#define F_WMRK0_MASK 0x01
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#define F_MODE_MASK 0xC0
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#define F_WMRK_MASK 0x3F
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#define F_MODE_DISABLED 0x00
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#define F_MODE_CIRCULAR (F_MODE0_MASK)
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#define F_MODE_FILL (F_MODE1_MASK)
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#define F_MODE_TRIGGER (F_MODE1_MASK + F_MODE0_MASK)
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/*
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* TRIG_CFG FIFO Trigger Configuration Register
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*/
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#define TRIG_CFG_REG 0x0A
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#define TRIG_TRANS_MASK 0x20
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#define TRIG_LNDPRT_MASK 0x10
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#define TRIG_PULSE_MASK 0x08
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#define TRIG_FF_MT_MASK 0x04
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/*
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* SYSMOD System Mode Register
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*/
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#define SYSMOD_REG 0x0B
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#define FGERR_MASK 0x80 /* MMA8451 only */
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#define FGT_4_MASK 0x40 /* MMA8451 only */
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#define FGT_3_MASK 0x20 /* MMA8451 only */
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#define FGT_2_MASK 0x10 /* MMA8451 only */
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#define FGT_1_MASK 0x08 /* MMA8451 only */
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#define FGT_0_MASK 0x04 /* MMA8451 only */
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#define FGT_MASK 0x7C /* MMA8451 only */
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#define SYSMOD1_MASK 0x02
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#define SYSMOD0_MASK 0x01
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#define SYSMOD_MASK 0x03
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#define SYSMOD_STANDBY 0x00
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#define SYSMOD_WAKE (SYSMOD0_MASK)
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#define SYSMOD_SLEEP (SYSMOD1_MASK)
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/*
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* INT_SOURCE System Interrupt Status Register
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*/
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#define INT_SOURCE_REG 0x0C
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#define SRC_ASLP_MASK 0x80
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#define SRC_FIFO_MASK 0x40
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#define SRC_TRANS_MASK 0x20
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#define SRC_LNDPRT_MASK 0x10
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#define SRC_PULSE_MASK 0x08
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#define SRC_FF_MT_MASK 0x04
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#define SRC_DRDY_MASK 0x01
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/*
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* WHO_AM_I Device ID Register
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*/
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#define WHO_AM_I_REG 0x0D
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/* Content */
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#define kFXOS_WHO_AM_I_Device_ID 0xC7U
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/* XYZ_DATA_CFG Sensor Data Configuration Register */
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#define XYZ_DATA_CFG_REG 0x0E
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#define HPF_OUT_MASK 0x10
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#define FS1_MASK 0x02
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#define FS0_MASK 0x01
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#define FS_MASK 0x03
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#define FULL_SCALE_2G 0x00
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#define FULL_SCALE_4G (FS0_MASK)
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#define FULL_SCALE_8G (FS1_MASK)
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/* HP_FILTER_CUTOFF High Pass Filter Register */
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#define HP_FILTER_CUTOFF_REG 0x0F
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#define PULSE_HPF_BYP_MASK 0x20
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#define PULSE_LPF_EN_MASK 0x10
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#define SEL1_MASK 0x02
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#define SEL0_MASK 0x01
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#define SEL_MASK 0x03
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/*
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* PL_STATUS Portrait/Landscape Status Register
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*/
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#define PL_STATUS_REG 0x10
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#define NEWLP_MASK 0x80
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#define LO_MASK 0x40
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#define LAPO1_MASK 0x04
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#define LAPO0_MASK 0x02
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#define BAFRO_MASK 0x01
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#define LAPO_MASK 0x06
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/*
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* PL_CFG Portrait/Landscape Configuration Register
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*/
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#define PL_CFG_REG 0x11
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#define DBCNTM_MASK 0x80
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#define PL_EN_MASK 0x40
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/*
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* PL_COUNT Portrait/Landscape Debounce Register
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*/
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#define PL_COUNT_REG 0x12
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/*
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* PL_BF_ZCOMP Back/Front and Z Compensation Register
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*/
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#define PL_BF_ZCOMP_REG 0x13
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#define BKFR1_MASK 0x80
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#define BKFR0_MASK 0x40
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#define ZLOCK2_MASK 0x04
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#define ZLOCK1_MASK 0x02
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#define ZLOCK0_MASK 0x01
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#define BKFR_MASK 0xC0
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#define ZLOCK_MASK 0x07
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/*
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* PL_P_L_THS Portrait to Landscape Threshold Register
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*/
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#define PL_P_L_THS_REG 0x14
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#define P_L_THS4_MASK 0x80
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#define P_L_THS3_MASK 0x40
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#define P_L_THS2_MASK 0x20
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#define P_L_THS1_MASK 0x10
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#define P_L_THS0_MASK 0x08
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#define HYS2_MASK 0x04
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#define HYS1_MASK 0x02
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#define HYS0_MASK 0x01
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#define P_L_THS_MASK 0xF8
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#define HYS_MASK 0x07
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/*
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* FF_MT_CFG Freefall and Motion Configuration Register
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*/
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#define FF_MT_CFG_REG 0x15
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#define ELE_MASK 0x80
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#define OAE_MASK 0x40
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#define ZEFE_MASK 0x20
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#define YEFE_MASK 0x10
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#define XEFE_MASK 0x08
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/*
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* FF_MT_SRC Freefall and Motion Source Registers
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*/
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#define FF_MT_SRC_REG 0x16
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#define EA_MASK 0x80
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#define ZHE_MASK 0x20
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#define ZHP_MASK 0x10
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#define YHE_MASK 0x08
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#define YHP_MASK 0x04
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#define XHE_MASK 0x02
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#define XHP_MASK 0x01
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/*
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* FF_MT_THS Freefall and Motion Threshold Registers
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* TRANSIENT_THS Transient Threshold Register
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*/
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#define FT_MT_THS_REG 0x17
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#define TRANSIENT_THS_REG 0x1F
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#define DBCNTM_MASK 0x80
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#define THS6_MASK 0x40
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#define THS5_MASK 0x20
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#define THS4_MASK 0x10
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#define THS3_MASK 0x08
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#define THS2_MASK 0x04
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#define TXS1_MASK 0x02
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#define THS0_MASK 0x01
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#define THS_MASK 0x7F
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/* FF_MT_COUNT Freefall Motion Count Registers */
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#define FF_MT_COUNT_REG 0x18
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/* TRANSIENT_CFG Transient Configuration Register */
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#define TRANSIENT_CFG_REG 0x1D
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#define TELE_MASK 0x10
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#define ZTEFE_MASK 0x08
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#define YTEFE_MASK 0x04
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#define XTEFE_MASK 0x02
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#define HPF_BYP_MASK 0x01
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/* TRANSIENT_SRC Transient Source Register */
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#define TRANSIENT_SRC_REG 0x1E
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#define TEA_MASK 0x40
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#define ZTRANSE_MASK 0x20
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#define Z_TRANS_POL_MASK 0x10
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#define YTRANSE_MASK 0x08
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#define Y_TRANS_POL_MASK 0x04
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#define XTRANSE_MASK 0x02
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#define X_TRANS_POL_MASK 0x01
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/* TRANSIENT_COUNT Transient Debounce Register */
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#define TRANSIENT_COUNT_REG 0x20
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/* PULSE_CFG Pulse Configuration Register */
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#define PULSE_CFG_REG 0x21
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#define DPA_MASK 0x80
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#define PELE_MASK 0x40
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#define ZDPEFE_MASK 0x20
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#define ZSPEFE_MASK 0x10
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#define YDPEFE_MASK 0x08
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#define YSPEFE_MASK 0x04
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#define XDPEFE_MASK 0x02
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#define XSPEFE_MASK 0x01
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/* PULSE_SRC Pulse Source Register */
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#define PULSE_SRC_REG 0x22
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#define PEA_MASK 0x80
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#define AXZ_MASK 0x40
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#define AXY_MASK 0x20
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#define AXX_MASK 0x10
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#define DPE_MASK 0x08
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#define POLZ_MASK 0x04
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#define POLY_MASK 0x02
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#define POLX_MASK 0x01
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/* PULSE_THS XYZ Pulse Threshold Registers */
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#define PULSE_THSX_REG 0x23
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#define PULSE_THSY_REG 0x24
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#define PULSE_THSZ_REG 0x25
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#define PTHS_MASK 0x7F
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/* PULSE_TMLT Pulse Time Window Register */
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#define PULSE_TMLT_REG 0x26
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/* PULSE_LTCY Pulse Latency Timer Register */
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#define PULSE_LTCY_REG 0x27
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/* PULSE_WIND Second Pulse Time Window Register */
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#define PULSE_WIND_REG 0x28
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/* ASLP_COUNT Auto Sleep Inactivity Timer Register */
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#define ASLP_COUNT_REG 0x29
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/* CTRL_REG1 System Control 1 Register */
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#define CTRL_REG1 0x2A
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#define ASLP_RATE1_MASK 0x80
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#define ASLP_RATE0_MASK 0x40
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#define DR2_MASK 0x20
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#define DR1_MASK 0x10
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#define DR0_MASK 0x08U
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#define LNOISE_MASK 0x04
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#define FREAD_MASK 0x02
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#define ACTIVE_MASK 0x01U
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#define ASLP_RATE_MASK 0xC0
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#define DR_MASK 0x38
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#define ASLP_RATE_20MS 0x00
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#define ASLP_RATE_80MS (ASLP_RATE0_MASK)
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#define ASLP_RATE_160MS (ASLP_RATE1_MASK)
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#define ASLP_RATE_640MS (ASLP_RATE1_MASK + ASLP_RATE0_MASK)
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#define ASLP_RATE_50HZ (ASLP_RATE_20MS)
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#define ASLP_RATE_12_5HZ (ASLP_RATE_80MS)
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#define ASLP_RATE_6_25HZ (ASLP_RATE_160MS)
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#define ASLP_RATE_1_56HZ (ASLP_RATE_640MS)
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#define HYB_ASLP_RATE_25HZ (ASLP_RATE_20MS)
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#define HYB_ASLP_RATE_6_25HZ (ASLP_RATE_80MS)
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#define HYB_ASLP_RATE_1_56HZ (ASLP_RATE_160MS)
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#define HYB_ASLP_RATE_0_8HZ (ASLP_RATE_640MS)
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#define DATA_RATE_1250US 0x00
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#define DATA_RATE_2500US (DR0_MASK)
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#define DATA_RATE_5MS (DR1_MASK)
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#define DATA_RATE_10MS (DR1_MASK + DR0_MASK)
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#define DATA_RATE_20MS (DR2_MASK)
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#define DATA_RATE_80MS (DR2_MASK + DR0_MASK)
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#define DATA_RATE_160MS (DR2_MASK + DR1_MASK)
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#define DATA_RATE_640MS (DR2_MASK + DR1_MASK + DR0_MASK)
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#define DATA_RATE_800HZ (DATA_RATE_1250US)
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#define DATA_RATE_400HZ (DATA_RATE_2500US)
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#define DATA_RATE_200HZ (DATA_RATE_5MS)
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#define DATA_RATE_100HZ (DATA_RATE_10MS)
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#define DATA_RATE_50HZ (DATA_RATE_20MS)
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#define DATA_RATE_12_5HZ (DATA_RATE_80MS)
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#define DATA_RATE_6_25HZ (DATA_RATE_160MS)
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#define DATA_RATE_1_56HZ (DATA_RATE_640MS)
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/* for hybrid (TO, Aug 2012) */
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#define HYB_DATA_RATE_400HZ (DATA_RATE_1250US)
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#define HYB_DATA_RATE_200HZ (DATA_RATE_2500US)
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#define HYB_DATA_RATE_100HZ (DATA_RATE_5MS)
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#define HYB_DATA_RATE_50HZ (DATA_RATE_10MS)
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#define HYB_DATA_RATE_25HZ (DATA_RATE_20MS)
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#define HYB_DATA_RATE_6_25HZ (DATA_RATE_80MS)
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#define HYB_DATA_RATE_3_15HZ (DATA_RATE_160MS)
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#define HYB_DATA_RATE_0_8HZ (DATA_RATE_640MS)
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#define ACTIVE (ACTIVE_MASK)
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#define STANDBY 0x00
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/* CTRL_REG2 System Control 2 Register */
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#define CTRL_REG2 0x2B
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#define ST_MASK 0x80
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#define RST_MASK 0x40
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#define SMODS1_MASK 0x10
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#define SMODS0_MASK 0x08
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#define SLPE_MASK 0x04
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#define MODS1_MASK 0x02
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#define MODS0_MASK 0x01
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#define SMODS_MASK 0x18
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#define MODS_MASK 0x03
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#define SMOD_NORMAL 0x00
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#define SMOD_LOW_NOISE (SMODS0_MASK)
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#define SMOD_HIGH_RES (SMODS1_MASK)
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#define SMOD_LOW_POWER (SMODS1_MASK + SMODS0_MASK)
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#define MOD_NORMAL 0x00
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#define MOD_LOW_NOISE (MODS0_MASK)
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#define MOD_HIGH_RES (MODS1_MASK)
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#define MOD_LOW_POWER (MODS1_MASK + MODS0_MASK)
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/* CTRL_REG3 Interrupt Control Register */
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#define CTRL_REG3 0x2C
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#define FIFO_GATE_MASK 0x80
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#define WAKE_TRANS_MASK 0x40
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#define WAKE_LNDPRT_MASK 0x20
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#define WAKE_PULSE_MASK 0x10
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#define WAKE_FF_MT_MASK 0x08
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#define IPOL_MASK 0x02
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#define PP_OD_MASK 0x01
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/* CTRL_REG4 Interrupt Enable Register */
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#define CTRL_REG4 0x2D
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#define INT_EN_ASLP_MASK 0x80
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#define INT_EN_FIFO_MASK 0x40
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#define INT_EN_TRANS_MASK 0x20
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#define INT_EN_LNDPRT_MASK 0x10
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#define INT_EN_PULSE_MASK 0x08
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#define INT_EN_FF_MT_MASK 0x04
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#define INT_EN_DRDY_MASK 0x01
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/* CTRL_REG5 Interrupt Configuration Register */
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#define CTRL_REG5 0x2E
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#define INT_CFG_ASLP_MASK 0x80
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#define INT_CFG_FIFO_MASK 0x40
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#define INT_CFG_TRANS_MASK 0x20
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#define INT_CFG_LNDPRT_MASK 0x10
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#define INT_CFG_PULSE_MASK 0x08
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#define INT_CFG_FF_MT_MASK 0x04
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#define INT_CFG_DRDY_MASK 0x01
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/* XYZ Offset Correction Registers */
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#define OFF_X_REG 0x2F
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#define OFF_Y_REG 0x30
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#define OFF_Z_REG 0x31
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/* M_DR_STATUS Register */
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#define M_DR_STATUS_REG 0x32
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#define ZYXOW_MASK 0x80
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#define ZOW_MASK 0x40
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#define YOW_MASK 0x20
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#define XOW_MASK 0x10
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#define ZYXDR_MASK 0x08
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#define ZDR_MASK 0x04
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#define YDR_MASK 0x02
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#define XDR_MASK 0x01
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/* MAG XYZ Data Registers */
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#define M_OUT_X_MSB_REG 0x33
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#define M_OUT_X_LSB_REG 0x34
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#define M_OUT_Y_MSB_REG 0x35
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#define M_OUT_Y_LSB_REG 0x36
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#define M_OUT_Z_MSB_REG 0x37
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#define M_OUT_Z_LSB_REG 0x38
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/* MAG CMP Data Registers */
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#define CMP_X_MSB_REG 0x39
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#define CMP_X_LSB_REG 0x3A
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#define CMP_Y_MSB_REG 0x3B
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#define CMP_Y_LSB_REG 0x3C
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#define CMP_Z_MSB_REG 0x3D
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#define CMP_Z_LSB_REG 0x3E
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/* MAG XYZ Offset Correction Registers */
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#define M_OFF_X_MSB_REG 0x3F
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#define M_OFF_X_LSB_REG 0x40
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#define M_OFF_Y_MSB_REG 0x41
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#define M_OFF_Y_LSB_REG 0x42
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#define M_OFF_Z_MSB_REG 0x43
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#define M_OFF_Z_LSB_REG 0x44
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/* MAG MAX XYZ Registers */
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#define MAX_X_MSB_REG 0x45
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#define MAX_X_LSB_REG 0x46
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#define MAX_Y_MSB_REG 0x47
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#define MAX_Y_LSB_REG 0x48
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#define MAX_Z_MSB_REG 0x49
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#define MAX_Z_LSB_REG 0x4A
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/* MAG MIN XYZ Registers */
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#define MIN_X_MSB_REG 0x4B
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#define MIN_X_LSB_REG 0x4C
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#define MIN_Y_MSB_REG 0x4D
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#define MIN_Y_LSB_REG 0x4E
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#define MIN_Z_MSB_REG 0x4F
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#define MIN_Z_LSB_REG 0x50
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/* TEMP Registers */
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#define TEMP_REG 0x51
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/* M_THS CONFIG Registers */
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#define M_THS_CFG_REG 0x52
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/* M_THS SRC Registers */
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#define M_THS_SRC_REG 0x53
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/* MAG THRESHOLD XYZ Registers */
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#define M_THS_X_MSB_REG 0x54
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#define M_THS_X_LSB_REG 0x55
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#define M_THS_Y_MSB_REG 0x56
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#define M_THS_Y_LSB_REG 0x57
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#define M_THS_Z_MSB_REG 0x58
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#define M_THS_Z_LSB_REG 0x59
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/* M_THS COUNT Registers */
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#define M_THS_COUNT 0x5A
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/* MAG CTRL_REG1 System Control 1 Register */
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#define M_CTRL_REG1 0x5B
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#define M_ACAL_MASK 0x80
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#define M_RST_MASK 0x40U
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#define M_OST_MASK 0x20
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#define M_OSR2_MASK 0x10
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#define M_OSR1_MASK 0x08
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#define M_OSR0_MASK 0x04
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#define M_HMS1_MASK 0x02
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#define M_HMS0_MASK 0x01
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#define M_OSR_MASK 0x1CU
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#define M_HMS_MASK 0x03U
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/* OSR Selections */
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#define M_OSR_1_56_HZ 0x00
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#define M_OSR_6_25_HZ M_OSR0_MASK
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#define M_OSR_12_5_HZ M_OSR1_MASK
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#define M_OSR_50_HZ M_OSR1_MASK + M_OSR0_MASK
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#define M_OSR_100_HZ M_OSR2_MASK
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#define M_OSR_200_HZ M_OSR2_MASK + M_OSR0_MASK
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#define M_OSR_400_HZ M_OSR2_MASK + M_OSR1_MASK
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#define M_OSR_800_HZ M_OSR2_MASK + M_OSR1_MASK + M_OSR0_MASK
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/* Hybrid Mode Selection */
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#define ACCEL_ACTIVE 0x00
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#define MAG_ACTIVE M_HMS0_MASK
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#define HYBRID_ACTIVE (M_HMS1_MASK | M_HMS0_MASK)
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/* MAG CTRL_REG2 System Control 2 Register */
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#define M_CTRL_REG2 0x5C
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#define M_HYB_AUTOINC_MASK 0x20
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#define M_MAXMIN_DIS_MASK 0x10
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#define M_MAXMIN_DIS_THS_MASK 0x08
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#define M_MAXMIN_RST_MASK 0x04
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#define M_RST_CNT1_MASK 0x02
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#define M_RST_CNT0_MASK 0x01
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/* Mag Auto-Reset De-Gauss Frequency */
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#define RST_ODR_CYCLE 0x00
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#define RST_16_ODR_CYCLE M_RST_CNT0_MASK
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#define RST_512_ODR_CYCLE M_RST_CNT1_MASK
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#define RST_DISABLED M_RST_CNT1_MASK + M_RST_CNT0_MASK
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/* MAG CTRL_REG3 System Control 3 Register */
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#define M_CTRL_REG3 0x5D
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#define M_RAW_MASK 0x80
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#define M_ASLP_OS_2_MASK 0x40
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#define M_ASLP_OS_1_MASK 0x20
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#define M_ASLP_OS_0_MASK 0x10
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#define M_THS_XYZ_MASK 0x08
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#define M_ST_Z_MASK 0x04
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#define M_ST_XY1_MASK 0x02
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#define M_ST_XY0_MASK 0x01
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#define M_ASLP_OSR_MASK 0x70
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#define M_ST_XY_MASK 0x03
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/* OSR Selections */
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#define M_ASLP_OSR_1_56_HZ 0x00
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#define M_ASLP_OSR_6_25_HZ M_ASLP_OS_0_MASK
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#define M_ASLP_OSR_12_5_HZ M_ASLP_OS_1_MASK
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#define M_ASLP_OSR_50_HZ M_ASLP_OS_1_MASK + M_ASLP_OS_0_MASK
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#define M_ASLP_OSR_100_HZ M_ASLP_OS_2_MASK
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#define M_ASLP_OSR_200_HZ M_ASLP_OS_2_MASK + M_ASLP_OS_0_MASK
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#define M_ASLP_OSR_400_HZ M_ASLP_OS_2_MASK + M_ASLP_OS_1_MASK
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#define M_ASLP_OSR_800_HZ M_ASLP_OS_2_MASK + M_ASLP_OS_1_MASK + M_ASLP_OS_0_MASK
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/* MAG INT SOURCE Register */
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#define M_INT_SOURCE 0x5E
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#define SRC_M_DRDY_MASK 0x04
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#define SRC_M_VECM_MASK 0x02
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#define SRC_M_THS_MASK 0x01
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/* ACCEL VECTOR CONFIG Register */
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#define A_VECM_CFG 0x5F
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#define A_VECM_INIT_CFG_MASK 0x40
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#define A_VECM_INIT_EN_MASK 0x20
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#define A_VECM_WAKE_EN_MASK 0x10
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#define A_VECM_EN_MASK 0x08
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#define A_VECM_UPDM_MASK 0x04
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#define A_VECM_INITM_MASK 0x02
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#define A_VECM_ELE_MASK 0x01
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/* ACCEL VECTOR THS MSB AND LSB Register */
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#define A_VECM_THS_MSB 0x60
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#define A_VECM_DBCNTM_MASK 0x80
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#define A_VECM_THS_LSB 0x61
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/* ACCEL VECTOR CNT Register */
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#define A_VECM_CNT 0x62
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/* ACCEL INITIAL XYZ VECTORS Register */
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#define A_VECM_INITX_MSB 0x63
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#define A_VECM_INITX_LSB 0x64
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#define A_VECM_INITY_MSB 0x65
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#define A_VECM_INITY_LSB 0x66
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#define A_VECM_INITZ_MSB 0x67
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#define A_VECM_INITZ_LSB 0x68
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/* MAG VECTOR CONFIG Register */
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#define M_VECM_CFG 0x69
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#define M_VECM_INIT_CFG_MASK 0x40
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#define M_VECM_INIT_EN_MASK 0x20
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#define M_VECM_WAKE_EN_MASK 0x10
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#define M_VECM_EN_MASK 0x08
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#define M_VECM_UPDM_MASK 0x04
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#define M_VECM_INITM_MASK 0x02
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#define M_VECM_ELE_MASK 0x01
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/* MAG VECTOR THS MSB AND LSB Register */
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#define M_VECM_THS_MSB 0x6A
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#define M_VECM_DBCNTM_MASK 0x80
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#define M_VECM_THS_LSB 0x6B
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/* MAG VECTOR CNT Register */
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#define M_VECM_CNT 0x6C
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/* MAG INITIAL XYZ VECTORS Register */
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#define M_VECM_INITX_MSB 0x6D
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#define M_VECM_INITX_LSB 0x6E
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#define M_VECM_INITY_MSB 0x6F
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#define M_VECM_INITY_LSB 0x70
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#define M_VECM_INITZ_MSB 0x71
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#define M_VECM_INITZ_LSB 0x72
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/* ACCEL FFMT THS X MSB AND LSB Register */
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#define A_FFMT_THS_X_MSB 0x73
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#define A_FFMT_THS_XYZ_EN_MASK 0x80
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#define A_FFMT_THS_X_LSB 0x74
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#define A_FFMT_THS_X_LSB_MASK 0xFC
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/* ACCEL FFMT THS Y MSB AND LSB Register */
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#define A_FFMT_THS_Y_MSB 0x75
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#define A_FFMT_THS_Y_EN_MASK 0x80
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#define A_FFMT_THS_Y_LSB 0x76
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#define A_FFMT_THS_Y_LSB_MASK 0xFC
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/* ACCEL FFMT THS Z MSB AND LSB Register */
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#define A_FFMT_THS_Z_MSB 0x77
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#define A_FFMT_THS_Z_EN_MASK 0x80
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#define A_FFMT_THS_Z_LSB 0x78
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#define A_FFMT_THS_Z_LSB_MASK 0xFC
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/* ACCEL TRANSIENT INIT Register */
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#define A_TRAN_INIT_XYZ_MSB 0x79
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#define A_TRAN_INIT_X_LSB 0x7A
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#define A_TRAN_INIT_Y_LSB 0x7B
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#define A_TRAN_INIT_Z_LSB 0x7C
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|
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/*! @brief Define I2C access function. */
|
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typedef status_t (*I2C_SendFunc_t)(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
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typedef status_t (*I2C_ReceiveFunc_t)(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
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|
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/*! @brief fxos8700cq configure definition. This structure should be global.*/
|
|
typedef struct _fxos_handle
|
|
{
|
|
/* Pointer to the user-defined I2C Send Data function. */
|
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I2C_SendFunc_t I2C_SendFunc;
|
|
/* Pointer to the user-defined I2C Receive Data function. */
|
|
I2C_ReceiveFunc_t I2C_ReceiveFunc;
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|
/* The I2C slave address . */
|
|
uint8_t slaveAddress;
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} fxos_handle_t;
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|
|
|
typedef struct _fxos8700cq_data
|
|
{
|
|
uint8_t accelXMSB;
|
|
uint8_t accelXLSB;
|
|
uint8_t accelYMSB;
|
|
uint8_t accelYLSB;
|
|
uint8_t accelZMSB;
|
|
uint8_t accelZLSB;
|
|
uint8_t magXMSB;
|
|
uint8_t magXLSB;
|
|
uint8_t magYMSB;
|
|
uint8_t magYLSB;
|
|
uint8_t magZMSB;
|
|
uint8_t magZLSB;
|
|
} fxos_data_t;
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|
|
|
/*! @brief fxos8700cq configure structure.*/
|
|
typedef struct _fxos_config
|
|
{
|
|
/* Pointer to the user-defined I2C Send Data function. */
|
|
I2C_SendFunc_t I2C_SendFunc;
|
|
/* Pointer to the user-defined I2C Receive Data function. */
|
|
I2C_ReceiveFunc_t I2C_ReceiveFunc;
|
|
/* The I2C slave address . */
|
|
uint8_t slaveAddress;
|
|
} fxos_config_t;
|
|
|
|
/*!
|
|
* @addtogroup fxos_common
|
|
* @{
|
|
*/
|
|
|
|
#if defined(__cplusplus)
|
|
extern "C" {
|
|
#endif
|
|
|
|
/*!
|
|
* @brief Verify and initialize fxos_handleice: Hybrid mode with ODR=50Hz, Mag OSR=32, Acc OSR=Normal.
|
|
*
|
|
* @param fxos_handle The pointer to accel driver handle.
|
|
* @param config The configuration structure pointer to accel.
|
|
*
|
|
* @return kStatus_Success if success or kStatus_Fail if error.
|
|
*/
|
|
status_t FXOS_Init(fxos_handle_t *fxos_handle, fxos_config_t *config);
|
|
|
|
/*!
|
|
* @brief Read data from sensors, assumes hyb_autoinc_mode is set in M_CTRL_REG2
|
|
*
|
|
* @param fxos_handle The pointer to accel driver handle.
|
|
* @param sensorData The pointer to the buffer to hold sensor data
|
|
*
|
|
* @return kStatus_Success if success or kStatus_Fail if error.
|
|
*/
|
|
status_t FXOS_ReadSensorData(fxos_handle_t *fxos_handle, fxos_data_t *sensorData);
|
|
|
|
/*!
|
|
* @brief Write value to register of sensor.
|
|
*
|
|
* @param handle The pointer to fxos8700cq driver handle.
|
|
* @param reg Register address.
|
|
* @param val Data want to write.
|
|
*
|
|
* @return kStatus_Success if success or kStatus_Fail if error.
|
|
*/
|
|
status_t FXOS_WriteReg(fxos_handle_t *handle, uint8_t reg, uint8_t val);
|
|
|
|
/*!
|
|
* @brief Read n bytes start at register from sensor.
|
|
*
|
|
* @param handle The pointer to fxos8700cq driver handle.
|
|
* @param reg Register address.
|
|
* @param val The pointer to address which store data.
|
|
* @param bytesNumber Number of bytes receiver.
|
|
*
|
|
* @return kStatus_Success if success or kStatus_Fail if error.
|
|
*/
|
|
status_t FXOS_ReadReg(fxos_handle_t *handle, uint8_t reg, uint8_t *val, uint8_t bytesNumber);
|
|
|
|
/*!
|
|
* @brief Get device accelerator resolution bits.
|
|
*
|
|
* @return accelerator resolution bits.
|
|
*/
|
|
static inline uint8_t FXOS_GetResolutionBits(void)
|
|
{
|
|
return FXOS8700CQ_ACCEL_RESOLUTION_BITS;
|
|
}
|
|
|
|
#if defined(__cplusplus)
|
|
}
|
|
#endif /* __cplusplus */
|
|
|
|
#endif /* _FSL_FXOS_H_ */
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