19 lines
440 B
C
19 lines
440 B
C
/*
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* Copyright 2022 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __FSL_ADAPTER_FLEXSPI_HYPER_FLASH_CONFIG_H__
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#define __FSL_ADAPTER_FLEXSPI_HYPER_FLASH_CONFIG_H__
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typedef enum
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{
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kHAL_Flash_Flexspi_Clock_High166M, /* Flexspi clock 332M, DDR mode, internal clock 166M. */
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kHAL_Flash_Flexspi_Clock_Low42M, /* Flexspi clock 83M, DDR mode, internal clock 42M. */
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} flexspi_clock_t;
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#endif
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