106 lines
3.7 KiB
C
106 lines
3.7 KiB
C
/* Dhara - NAND flash management layer
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* Copyright (C) 2013 Daniel Beer <dlbeer@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef DHARA_NAND_H_
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#define DHARA_NAND_H_
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#include <stdint.h>
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#include <stddef.h>
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#include "error.h"
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/* Each page in a NAND device is indexed, starting at 0. It's required
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* that there be a power-of-two number of pages in a eraseblock, so you can
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* view a page number is being a concatenation (in binary) of a block
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* number and the number of a page within a block.
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*/
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typedef uint32_t dhara_page_t;
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/* Blocks are also indexed, starting at 0. */
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typedef uint32_t dhara_block_t;
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/* Each NAND chip must be represented by one of these structures. It's
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* intended that this structure be embedded in a larger structure for
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* context.
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*
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* The functions declared below are not implemented -- they must be
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* provided and satisfy the documented conditions.
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*/
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struct dhara_nand {
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/* Base-2 logarithm of the page size. If your device supports
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* partial programming, you may want to subdivide the actual
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* pages into separate ECC-correctable regions and present those
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* as pages.
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*/
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uint8_t log2_page_size;
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/* Base-2 logarithm of the number of pages within an eraseblock */
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uint8_t log2_ppb;
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/* Total number of eraseblocks */
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unsigned int num_blocks;
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};
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/* Is the given block bad? */
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int dhara_nand_is_bad(const struct dhara_nand *n, dhara_block_t b);
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/* Mark bad the given block (or attempt to). No return value is
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* required, because there's nothing that can be done in response.
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*/
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void dhara_nand_mark_bad(const struct dhara_nand *n, dhara_block_t b);
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/* Erase the given block. This function should return 0 on success or -1
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* on failure.
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*
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* The status reported by the chip should be checked. If an erase
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* operation fails, return -1 and set err to E_BAD_BLOCK.
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*/
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int dhara_nand_erase(const struct dhara_nand *n, dhara_block_t b,
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dhara_error_t *err);
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/* Program the given page. The data pointer is a pointer to an entire
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* page ((1 << log2_page_size) bytes). The operation status should be
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* checked. If the operation fails, return -1 and set err to
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* E_BAD_BLOCK.
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*
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* Pages will be programmed sequentially within a block, and will not be
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* reprogrammed.
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*/
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int dhara_nand_prog(const struct dhara_nand *n, dhara_page_t p,
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const uint8_t *data,
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dhara_error_t *err);
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/* Check that the given page is erased */
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int dhara_nand_is_free(const struct dhara_nand *n, dhara_page_t p);
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/* Read a portion of a page. ECC must be handled by the NAND
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* implementation. Returns 0 on sucess or -1 if an error occurs. If an
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* uncorrectable ECC error occurs, return -1 and set err to E_ECC.
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*/
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int dhara_nand_read(const struct dhara_nand *n, dhara_page_t p,
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size_t offset, size_t length,
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uint8_t *data,
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dhara_error_t *err);
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/* Read a page from one location and reprogram it in another location.
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* This might be done using the chip's internal buffers, but it must use
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* ECC.
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*/
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int dhara_nand_copy(const struct dhara_nand *n,
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dhara_page_t src, dhara_page_t dst,
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dhara_error_t *err);
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#endif
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