diff --git a/devices/MK60D10/drivers/fsl_enet.c b/devices/MK60D10/drivers/fsl_enet.c
index b4f7dc6..4ac832c 100644
--- a/devices/MK60D10/drivers/fsl_enet.c
+++ b/devices/MK60D10/drivers/fsl_enet.c
@@ -540,7 +540,7 @@ static void ENET_SetMacController(ENET_Type *base,
     ecr |= ENET_ECR_EN1588_MASK;
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
     /* Enables Ethernet module after all configuration except the buffer descriptor active. */
-    ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK;
+    ecr |= ENET_ECR_ETHEREN_MASK; /* Rev.1 HW does not support descriptor swapping. */
     base->ECR = ecr;
 }
 
@@ -558,9 +558,9 @@ static void ENET_SetTxBufferDescriptors(volatile enet_tx_bd_struct_t *txBdStartA
     for (count = 0; count < txBdNumber; count++)
     {
         /* Set data buffer address. */
-        curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]);
+        curBuffDescrip->buffer = ENET_CPU_TO_BEADDR((uint32_t)&txBuffStartAlign[count * txBuffSizeAlign]);
         /* Initializes data length. */
-        curBuffDescrip->length = 0;
+        curBuffDescrip->length = ENET_CPU_TO_BE16(0);
         /* Sets the crc. */
         curBuffDescrip->control = ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK;
         /* Sets the last buffer descriptor with the wrap flag. */
@@ -594,8 +594,8 @@ static void ENET_SetRxBufferDescriptors(volatile enet_rx_bd_struct_t *rxBdStartA
     for (count = 0; count < rxBdNumber; count++)
     {
         /* Set data buffer and the length. */
-        curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffStartAlign[count * rxBuffSizeAlign]);
-        curBuffDescrip->length = 0;
+        curBuffDescrip->buffer = ENET_CPU_TO_BEADDR((uint32_t)&rxBuffStartAlign[count * rxBuffSizeAlign]);
+        curBuffDescrip->length = ENET_CPU_TO_BE16(0);
 
         /* Initializes the buffer descriptors with empty bit. */
         curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK;
@@ -866,7 +866,7 @@ status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length)
                 return kStatus_ENET_RxFrameError;
             }
             /* FCS is removed by MAC. */
-            *length = curBuffDescrip->length;
+            *length = ENET_BE16_TO_CPU(curBuffDescrip->length);
             return kStatus_Success;
         }
         /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */
@@ -935,11 +935,11 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
             {
                 /* This is a valid frame. */
                 isLastBuff = true;
-                if (length == curBuffDescrip->length)
+                if (length == ENET_BE16_TO_CPU(curBuffDescrip->length))
                 {
                     /* Copy the frame to user's buffer without FCS. */
-                    len = curBuffDescrip->length - offset;
-                    memcpy(data + offset, curBuffDescrip->buffer, len);
+                    len = ENET_BE16_TO_CPU(curBuffDescrip->length) - offset;
+                    memcpy(data + offset, ENET_BEADDR_TO_CPU(curBuffDescrip->buffer), len);
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
                     /* Store the PTP 1588 timestamp for received PTP event frame. */
                     if (isPtpEventMessage)
@@ -970,7 +970,7 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
                     break;
                 }
 
-                memcpy(data + offset, curBuffDescrip->buffer, handle->rxBuffSizeAlign);
+                memcpy(data + offset, ENET_BEADDR_TO_CPU(curBuffDescrip->buffer), handle->rxBuffSizeAlign);
                 offset += handle->rxBuffSizeAlign;
 
                 /* Updates the receive buffer descriptors. */
@@ -1033,9 +1033,9 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
     if (handle->txBuffSizeAlign >= length)
     {
         /* Copy data to the buffer for uDMA transfer. */
-        memcpy(curBuffDescrip->buffer, data, length);
+        memcpy(ENET_BEADDR_TO_CPU(curBuffDescrip->buffer), data, length);
         /* Set data length. */
-        curBuffDescrip->length = length;
+        curBuffDescrip->length = ENET_CPU_TO_BE16(length);
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
         /* For enable the timestamp. */
         if (isPtpEventMessage)
@@ -1095,9 +1095,9 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
             if (sizeleft > handle->txBuffSizeAlign)
             {
                 /* Data copy. */
-                memcpy(curBuffDescrip->buffer, data + len, handle->txBuffSizeAlign);
+                memcpy(ENET_BEADDR_TO_CPU(curBuffDescrip->buffer), data + len, handle->txBuffSizeAlign);
                 /* Data length update. */
-                curBuffDescrip->length = handle->txBuffSizeAlign;
+                curBuffDescrip->length = ENET_CPU_TO_BE16(handle->txBuffSizeAlign);
                 len += handle->txBuffSizeAlign;
                 /* Sets the control flag. */
                 curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
@@ -1107,8 +1107,8 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
             }
             else
             {
-                memcpy(curBuffDescrip->buffer, data + len, sizeleft);
-                curBuffDescrip->length = sizeleft;
+                memcpy(ENET_BEADDR_TO_CPU(curBuffDescrip->buffer), data + len, sizeleft);
+                curBuffDescrip->length = ENET_CPU_TO_BE16(sizeleft);
                 /* Set Last buffer wrap flag. */
                 curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
                 /* Active the transmit buffer descriptor. */
diff --git a/devices/MK60D10/drivers/fsl_enet.h b/devices/MK60D10/drivers/fsl_enet.h
index db1b947..1ff2813 100644
--- a/devices/MK60D10/drivers/fsl_enet.h
+++ b/devices/MK60D10/drivers/fsl_enet.h
@@ -50,29 +50,30 @@
 
 /*! @name Control and status region bit masks of the receive buffer descriptor. */
 /*@{*/
-#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U       /*!< Empty bit mask. */
-#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U  /*!< Software owner one mask. */
-#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U        /*!< Next buffer descriptor is the start address. */
-#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U  /*!< Software owner two mask. */
-#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U        /*!< Last BD of the frame mask. */
-#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U        /*!< Received because of the promiscuous mode. */
-#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U   /*!< Broadcast packet mask. */
-#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U   /*!< Multicast packet mask. */
-#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */
-#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U     /*!< Non-octet aligned frame mask. */
-#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U         /*!< CRC error mask. */
-#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U     /*!< FIFO overrun mask. */
-#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U       /*!< Frame is truncated mask. */
+/*! @brief For Rev. 1.x devices, the byte order is reversed. */
+#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x80U         /*!< Empty bit mask. */
+#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x40U    /*!< Software owner one mask. */
+#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x20U          /*!< Next buffer descriptor is the start address. */
+#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x10U    /*!< Software owner two mask. */
+#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x08U          /*!< Last BD of the frame mask. */
+#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x01U          /*!< Received because of the promiscuous mode. */
+#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x8000U   /*!< Broadcast packet mask. */
+#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x4000U   /*!< Multicast packet mask. */
+#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x2000U /*!< Length violation mask. */
+#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x1000U     /*!< Non-octet aligned frame mask. */
+#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0400U         /*!< CRC error mask. */
+#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0200U     /*!< FIFO overrun mask. */
+#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0100U       /*!< Frame is truncated mask. */
 /*@}*/
 
 /*! @name Control and status bit masks of the transmit buffer descriptor. */
 /*@{*/
-#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U       /*!< Ready bit mask. */
-#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */
-#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U        /*!< Wrap buffer descriptor mask. */
-#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */
-#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U        /*!< Last BD of the frame mask. */
-#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U  /*!< Transmit CRC mask. */
+#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x80U         /*!< Ready bit mask. */
+#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x40U   /*!< Software owner one mask. */
+#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x20U          /*!< Wrap buffer descriptor mask. */
+#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x10U   /*!< Software owner two mask. */
+#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x08U          /*!< Last BD of the frame mask. */
+#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x04U    /*!< Transmit CRC mask. */
 /*@}*/
 
 /* Extended control regions for enhanced buffer descriptors. */
@@ -139,6 +140,21 @@
 /*! @brief Defines the PHY address scope for the ENET. */
 #define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT)
 
+/*! @brief Swap LE to BE for Rev. 1.x devices. */
+#define ENET_BE16_TO_CPU(x) (uint16_t)(((uint16_t)x << 8U) | ((uint16_t)x >> 8U))
+#define ENET_CPU_TO_BE16(x) ENET_BE16_TO_CPU(x)
+
+#define ENET_BEADDR_TO_CPU(x) (unsigned char *)(((uint32_t)(x) >> 24) \
+                              | (((uint32_t)(x) >> 8) & 0x0000ff00) \
+                              | (((uint32_t)(x) << 8) & 0x00ff0000) \
+                              | (((uint32_t)(x) << 24) & 0xff000000))
+
+#define ENET_CPU_TO_BEADDR(x) (uint32_t)(((uint32_t)(x) >> 24) \
+                              | (((uint32_t)(x) >> 8) & 0x0000ff00) \
+                              | (((uint32_t)(x) << 8) & 0x00ff0000) \
+                              | (((uint32_t)(x) << 24) & 0xff000000))
+
+
 /*! @brief Defines the status return codes for transaction. */
 enum _enet_status
 {
@@ -319,9 +335,9 @@ typedef enum _enet_ptp_timer_channel_mode
 /*! @brief Defines the receive buffer descriptor structure for the little endian system.*/
 typedef struct _enet_rx_bd_struct
 {
-    uint16_t length;  /*!< Buffer descriptor data length. */
     uint16_t control; /*!< Buffer descriptor control and status. */
-    uint8_t *buffer;  /*!< Data buffer pointer. */
+    uint16_t length;  /*!< Buffer descriptor data length. */
+    uint32_t buffer;  /*!< Data buffer pointer. */
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
     uint16_t controlExtend0;  /*!< Extend buffer descriptor control0. */
     uint16_t controlExtend1;  /*!< Extend buffer descriptor control1. */
@@ -341,9 +357,9 @@ typedef struct _enet_rx_bd_struct
 /*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */
 typedef struct _enet_tx_bd_struct
 {
-    uint16_t length;  /*!< Buffer descriptor data length. */
     uint16_t control; /*!< Buffer descriptor control and status. */
-    uint8_t *buffer;  /*!< Data buffer pointer. */
+    uint16_t length;  /*!< Buffer descriptor data length. */
+    uint32_t buffer;  /*!< Data buffer pointer. */
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
     uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */
     uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */