Updated flexbus driver, changed file permission on SIM.
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ebf85f1dc6
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@ -1,35 +1,18 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexbus.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexbus"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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@ -77,13 +60,36 @@ static uint32_t FLEXBUS_GetInstance(FB_Type *base)
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return instance;
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}
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/*!
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* brief Initializes and configures the FlexBus module.
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*
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* This function enables the clock gate for FlexBus module.
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* Only chip 0 is validated and set to known values. Other chips are disabled.
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* Note that in this function, certain parameters, depending on external memories, must
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* be set before using the FLEXBUS_Init() function.
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* This example shows how to set up the uart_state_t and the
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* flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
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* in these parameters.
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code
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flexbus_config_t flexbusConfig;
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FLEXBUS_GetDefaultConfig(&flexbusConfig);
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flexbusConfig.waitStates = 2U;
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flexbusConfig.chipBaseAddress = 0x60000000U;
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flexbusConfig.chipBaseAddressMask = 7U;
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FLEXBUS_Init(FB, &flexbusConfig);
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endcode
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*
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* param base FlexBus peripheral address.
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* param config Pointer to the configuration structure
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*/
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void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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{
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assert(config != NULL);
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assert(config->chip < FB_CSAR_COUNT);
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assert(config->waitStates <= 0x3FU);
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assert(config->secondaryWaitStates <= 0x3FU);
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uint32_t chip = config->chip;
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uint32_t chip = config->chip;
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uint32_t reg_value = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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@ -91,8 +97,8 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset the corresponding register to default state */
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/* Reset CSMR register, all chips not valid (disabled) */
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/* Reset the associated register to default state */
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/* Set CSMR register, all chips not valid (disabled) */
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base->CS[chip].CSMR = 0x0000U;
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/* Set default base address */
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base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
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@ -101,43 +107,42 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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/* Set FB_CSPMCR register */
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/* FlexBus signal group 1 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
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/* FlexBus signal group 2 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
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/* FlexBus signal group 3 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
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/* FlexBus signal group 4 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
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/* FlexBus signal group 5 multiplex control */
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reg_value |= kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
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/* Write to CSPMCR register */
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base->CSPMCR = reg_value;
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/* Update chip value */
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chip = config->chip;
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/* Base address */
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reg_value = config->chipBaseAddress;
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/* Write to CSAR register */
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base->CS[chip].CSAR = reg_value;
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/* Chip-select validation */
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reg_value = 0x1U << FB_CSMR_V_SHIFT;
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/* Write protect */
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reg_value |= (uint32_t)(config->writeProtect) << FB_CSMR_WP_SHIFT;
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reg_value |= ((uint32_t)config->writeProtect) << FB_CSMR_WP_SHIFT;
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/* Base address mask */
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reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT;
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/* Write to CSMR register */
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base->CS[chip].CSMR = reg_value;
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/* Burst write */
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reg_value = (uint32_t)(config->burstWrite) << FB_CSCR_BSTW_SHIFT;
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reg_value = ((uint32_t)config->burstWrite) << FB_CSCR_BSTW_SHIFT;
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/* Burst read */
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reg_value |= (uint32_t)(config->burstRead) << FB_CSCR_BSTR_SHIFT;
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reg_value |= ((uint32_t)config->burstRead) << FB_CSCR_BSTR_SHIFT;
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/* Byte-enable mode */
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reg_value |= (uint32_t)(config->byteEnableMode) << FB_CSCR_BEM_SHIFT;
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reg_value |= ((uint32_t)config->byteEnableMode) << FB_CSCR_BEM_SHIFT;
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/* Port size */
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reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT;
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/* The internal transfer acknowledge for accesses */
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reg_value |= (uint32_t)(config->autoAcknowledge) << FB_CSCR_AA_SHIFT;
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reg_value |= ((uint32_t)config->autoAcknowledge) << FB_CSCR_AA_SHIFT;
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/* Byte-Lane shift */
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reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT;
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/* The number of wait states */
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@ -149,11 +154,16 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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/* Address setup */
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reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT;
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/* Extended transfer start/extended address latch */
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reg_value |= (uint32_t)(config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;
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reg_value |= ((uint32_t)config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;
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/* Secondary wait state */
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reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWSEN_SHIFT;
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if (config->secondaryWaitStatesEnable)
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{
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reg_value |= FB_CSCR_SWSEN_MASK;
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reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWS_SHIFT;
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}
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/* Write to CSCR register */
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base->CS[chip].CSCR = reg_value;
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/* FlexBus signal group 1 multiplex control */
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reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;
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/* FlexBus signal group 2 multiplex control */
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@ -166,8 +176,21 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;
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/* Write to CSPMCR register */
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base->CSPMCR = reg_value;
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/* Enable CSPMCR0[V] to make all chip select registers take effect. */
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if (chip != 0UL)
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{
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base->CS[0].CSMR |= FB_CSMR_V_MASK;
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}
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}
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/*!
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* brief De-initializes a FlexBus instance.
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*
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* This function disables the clock gate of the FlexBus module clock.
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*
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* param base FlexBus peripheral address.
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*/
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void FLEXBUS_Deinit(FB_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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@ -176,25 +199,56 @@ void FLEXBUS_Deinit(FB_Type *base)
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Initializes the FlexBus configuration structure.
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*
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* This function initializes the FlexBus configuration structure to default value. The default
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* values are.
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code
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fbConfig->chip = 0;
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fbConfig->writeProtect = false;
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fbConfig->burstWrite = false;
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fbConfig->burstRead = false;
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fbConfig->byteEnableMode = false;
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fbConfig->autoAcknowledge = true;
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fbConfig->extendTransferAddress = false;
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fbConfig->secondaryWaitStatesEnable = false;
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fbConfig->byteLaneShift = kFLEXBUS_NotShifted;
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fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle;
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fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles;
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fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge;
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fbConfig->portSize = kFLEXBUS_1Byte;
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fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE;
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fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ;
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fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5;
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fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST;
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fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA;
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endcode
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* param config Pointer to the initialization structure.
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* see FLEXBUS_Init
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*/
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void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)
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{
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config->chip = 0; /* Chip 0 FlexBus for validation */
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config->writeProtect = 0; /* Write accesses are allowed */
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config->burstWrite = 0; /* Burst-Write disable */
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config->burstRead = 0; /* Burst-Read disable */
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config->byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */
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config->autoAcknowledge = true; /* Auto-Acknowledge enable */
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config->extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */
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config->secondaryWaitStates = 0; /* Secondary wait state disable */
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config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */
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config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */
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config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->chip = 0; /* Chip 0 FlexBus for validation */
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config->writeProtect = false; /* Write accesses are allowed */
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config->burstWrite = false; /* Burst-Write disable */
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config->burstRead = false; /* Burst-Read disable */
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config->byteEnableMode = false; /* Byte-Enable mode is asserted for data write only */
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config->autoAcknowledge = true; /* Auto-Acknowledge enable */
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config->extendTransferAddress = false; /* Extend transfer start/extend address latch disable */
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config->secondaryWaitStatesEnable = false; /* Secondary wait state disable */
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config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */
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config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */
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config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */
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config->addressSetup =
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kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */
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config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */
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kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */
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config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */
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config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */
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config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */
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config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */
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config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */
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config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */
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}
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}
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@ -1,31 +1,9 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_FLEXBUS_H_
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
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/*@}*/
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#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */
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/*@}*/
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/*!
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* @brief Defines port size for FlexBus peripheral.
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@ -54,7 +31,7 @@
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typedef enum _flexbus_port_size
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{
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kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */
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kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */
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kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */
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kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */
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} flexbus_port_size_t;
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@ -63,7 +40,7 @@ typedef enum _flexbus_port_size
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*/
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typedef enum _flexbus_write_address_hold
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{
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kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */
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kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */
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kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */
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kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */
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kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */
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@ -76,8 +53,8 @@ typedef enum _flexbus_read_address_hold
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{
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kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */
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kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */
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kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */
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kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */
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kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */
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kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */
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} flexbus_read_address_hold_t;
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/*!
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@ -85,9 +62,9 @@ typedef enum _flexbus_read_address_hold
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*/
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typedef enum _flexbus_address_setup
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{
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kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */
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kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */
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kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */
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kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */
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kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */
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kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */
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} flexbus_address_setup_t;
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@ -97,7 +74,7 @@ typedef enum _flexbus_address_setup
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typedef enum _flexbus_bytelane_shift
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{
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kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */
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kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */
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kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */
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} flexbus_bytelane_shift_t;
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/*!
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@ -107,7 +84,7 @@ typedef enum _flexbus_multiplex_group1_signal
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{
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kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */
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kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */
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kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */
|
||||
kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */
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||||
} flexbus_multiplex_group1_t;
|
||||
|
||||
/*!
|
||||
|
@ -115,8 +92,8 @@ typedef enum _flexbus_multiplex_group1_signal
|
|||
*/
|
||||
typedef enum _flexbus_multiplex_group2_signal
|
||||
{
|
||||
kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */
|
||||
kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */
|
||||
kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */
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kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */
|
||||
kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */
|
||||
} flexbus_multiplex_group2_t;
|
||||
|
||||
|
@ -125,8 +102,8 @@ typedef enum _flexbus_multiplex_group2_signal
|
|||
*/
|
||||
typedef enum _flexbus_multiplex_group3_signal
|
||||
{
|
||||
kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */
|
||||
kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */
|
||||
kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */
|
||||
kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */
|
||||
kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */
|
||||
} flexbus_multiplex_group3_t;
|
||||
|
||||
|
@ -135,8 +112,8 @@ typedef enum _flexbus_multiplex_group3_signal
|
|||
*/
|
||||
typedef enum _flexbus_multiplex_group4_signal
|
||||
{
|
||||
kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */
|
||||
kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */
|
||||
kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */
|
||||
kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */
|
||||
kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */
|
||||
} flexbus_multiplex_group4_t;
|
||||
|
||||
|
@ -145,8 +122,8 @@ typedef enum _flexbus_multiplex_group4_signal
|
|||
*/
|
||||
typedef enum _flexbus_multiplex_group5_signal
|
||||
{
|
||||
kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */
|
||||
kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */
|
||||
kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */
|
||||
kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */
|
||||
kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */
|
||||
} flexbus_multiplex_group5_t;
|
||||
|
||||
|
@ -157,6 +134,7 @@ typedef struct _flexbus_config
|
|||
{
|
||||
uint8_t chip; /*!< Chip FlexBus for validation */
|
||||
uint8_t waitStates; /*!< Value of wait states */
|
||||
uint8_t secondaryWaitStates; /*!< Value of secondary wait states */
|
||||
uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */
|
||||
uint32_t chipBaseAddressMask; /*!< Chip base address mask */
|
||||
bool writeProtect; /*!< Write protected */
|
||||
|
@ -165,7 +143,7 @@ typedef struct _flexbus_config
|
|||
bool byteEnableMode; /*!< Byte-enable mode support */
|
||||
bool autoAcknowledge; /*!< Auto acknowledge setting */
|
||||
bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */
|
||||
bool secondaryWaitStates; /*!< Secondary wait states number */
|
||||
bool secondaryWaitStatesEnable; /*!< Enable secondary wait states */
|
||||
flexbus_port_size_t portSize; /*!< Port size of transfer */
|
||||
flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */
|
||||
flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */
|
||||
|
@ -262,4 +240,4 @@ void FLEXBUS_GetDefaultConfig(flexbus_config_t *config);
|
|||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_FLEXBUS_H_ */
|
||||
#endif /* _FSL_FLEXBUS_H_ */
|
Loading…
Reference in New Issue