diff --git a/devices/MK60D10/drivers/fsl_flexbus.c b/devices/MK60D10/drivers/fsl_flexbus.c
index 4a179b1..3aa192a 100644
--- a/devices/MK60D10/drivers/fsl_flexbus.c
+++ b/devices/MK60D10/drivers/fsl_flexbus.c
@@ -83,7 +83,7 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
     assert(config->chip < FB_CSAR_COUNT);
     assert(config->waitStates <= 0x3FU);
 
-    uint32_t chip = 0;
+    uint32_t chip = config->chip;
     uint32_t reg_value = 0;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -91,16 +91,14 @@ void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
     CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-    /* Reset all the register to default state */
-    for (chip = 0; chip < FB_CSAR_COUNT; chip++)
-    {
-        /* Reset CSMR register, all chips not valid (disabled) */
-        base->CS[chip].CSMR = 0x0000U;
-        /* Set default base address */
-        base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
-        /* Reset FB_CSCRx register */
-        base->CS[chip].CSCR = 0x0000U;
-    }
+    /* Reset the corresponding register to default state */
+    /* Reset CSMR register, all chips not valid (disabled) */
+    base->CS[chip].CSMR = 0x0000U;
+    /* Set default base address */
+    base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
+    /* Reset FB_CSCRx register */
+    base->CS[chip].CSCR = 0x0000U;
+
     /* Set FB_CSPMCR register */
     /* FlexBus signal group 1 multiplex control */
     reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;