254 lines
11 KiB
C
254 lines
11 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_flexbus.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexbus"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address
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*
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* @param base FLEXBUS peripheral base address
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*
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* @return The FLEXBUS instance
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*/
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static uint32_t FLEXBUS_GetInstance(FB_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to FLEXBUS bases for each instance. */
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static FB_Type *const s_flexbusBases[] = FB_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to FLEXBUS clocks for each instance. */
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static const clock_ip_name_t s_flexbusClocks[] = FLEXBUS_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t FLEXBUS_GetInstance(FB_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_flexbusBases); instance++)
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{
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if (s_flexbusBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_flexbusBases));
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return instance;
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}
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/*!
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* brief Initializes and configures the FlexBus module.
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*
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* This function enables the clock gate for FlexBus module.
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* Only chip 0 is validated and set to known values. Other chips are disabled.
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* Note that in this function, certain parameters, depending on external memories, must
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* be set before using the FLEXBUS_Init() function.
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* This example shows how to set up the uart_state_t and the
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* flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing
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* in these parameters.
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code
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flexbus_config_t flexbusConfig;
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FLEXBUS_GetDefaultConfig(&flexbusConfig);
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flexbusConfig.waitStates = 2U;
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flexbusConfig.chipBaseAddress = 0x60000000U;
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flexbusConfig.chipBaseAddressMask = 7U;
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FLEXBUS_Init(FB, &flexbusConfig);
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endcode
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*
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* param base FlexBus peripheral address.
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* param config Pointer to the configuration structure
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*/
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void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config)
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{
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assert(config != NULL);
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assert(config->chip < FB_CSAR_COUNT);
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assert(config->waitStates <= 0x3FU);
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assert(config->secondaryWaitStates <= 0x3FU);
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uint32_t chip = config->chip;
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uint32_t reg_value = 0;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate clock for FLEXBUS */
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CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Reset the associated register to default state */
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/* Set CSMR register, all chips not valid (disabled) */
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base->CS[chip].CSMR = 0x0000U;
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/* Set default base address */
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base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK);
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/* Reset FB_CSCRx register */
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base->CS[chip].CSCR = 0x0000U;
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/* Set FB_CSPMCR register */
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/* FlexBus signal group 1 multiplex control */
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT;
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/* FlexBus signal group 2 multiplex control */
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT;
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/* FlexBus signal group 3 multiplex control */
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT;
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/* FlexBus signal group 4 multiplex control */
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT;
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/* FlexBus signal group 5 multiplex control */
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reg_value |= (uint32_t)kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT;
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/* Write to CSPMCR register */
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base->CSPMCR = reg_value;
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/* Base address */
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reg_value = config->chipBaseAddress;
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/* Write to CSAR register */
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base->CS[chip].CSAR = reg_value;
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/* Chip-select validation */
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reg_value = 0x1U << FB_CSMR_V_SHIFT;
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/* Write protect */
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reg_value |= ((uint32_t)config->writeProtect) << FB_CSMR_WP_SHIFT;
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/* Base address mask */
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reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT;
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/* Write to CSMR register */
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base->CS[chip].CSMR = reg_value;
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/* Burst write */
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reg_value = ((uint32_t)config->burstWrite) << FB_CSCR_BSTW_SHIFT;
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/* Burst read */
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reg_value |= ((uint32_t)config->burstRead) << FB_CSCR_BSTR_SHIFT;
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/* Byte-enable mode */
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reg_value |= ((uint32_t)config->byteEnableMode) << FB_CSCR_BEM_SHIFT;
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/* Port size */
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reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT;
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/* The internal transfer acknowledge for accesses */
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reg_value |= ((uint32_t)config->autoAcknowledge) << FB_CSCR_AA_SHIFT;
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/* Byte-Lane shift */
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reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT;
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/* The number of wait states */
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reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT;
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/* Write address hold or deselect */
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reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT;
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/* Read address hold or deselect */
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reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT;
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/* Address setup */
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reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT;
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/* Extended transfer start/extended address latch */
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reg_value |= ((uint32_t)config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT;
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/* Secondary wait state */
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if (config->secondaryWaitStatesEnable)
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{
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reg_value |= FB_CSCR_SWSEN_MASK;
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reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWS_SHIFT;
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}
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/* Write to CSCR register */
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base->CS[chip].CSCR = reg_value;
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/* FlexBus signal group 1 multiplex control */
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reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT;
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/* FlexBus signal group 2 multiplex control */
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reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT;
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/* FlexBus signal group 3 multiplex control */
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reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT;
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/* FlexBus signal group 4 multiplex control */
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reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT;
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/* FlexBus signal group 5 multiplex control */
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reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT;
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/* Write to CSPMCR register */
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base->CSPMCR = reg_value;
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/* Enable CSPMCR0[V] to make all chip select registers take effect. */
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if (chip != 0UL)
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{
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base->CS[0].CSMR |= FB_CSMR_V_MASK;
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}
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}
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/*!
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* brief De-initializes a FlexBus instance.
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*
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* This function disables the clock gate of the FlexBus module clock.
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*
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* param base FlexBus peripheral address.
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*/
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void FLEXBUS_Deinit(FB_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate clock for FLEXBUS */
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CLOCK_DisableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Initializes the FlexBus configuration structure.
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*
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* This function initializes the FlexBus configuration structure to default value. The default
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* values are.
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code
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fbConfig->chip = 0;
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fbConfig->writeProtect = false;
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fbConfig->burstWrite = false;
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fbConfig->burstRead = false;
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fbConfig->byteEnableMode = false;
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fbConfig->autoAcknowledge = true;
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fbConfig->extendTransferAddress = false;
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fbConfig->secondaryWaitStatesEnable = false;
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fbConfig->byteLaneShift = kFLEXBUS_NotShifted;
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fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle;
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fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles;
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fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge;
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fbConfig->portSize = kFLEXBUS_1Byte;
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fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE;
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fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ;
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fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5;
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fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST;
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fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA;
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endcode
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* param config Pointer to the initialization structure.
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* see FLEXBUS_Init
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*/
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void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)
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{
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->chip = 0; /* Chip 0 FlexBus for validation */
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config->writeProtect = false; /* Write accesses are allowed */
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config->burstWrite = false; /* Burst-Write disable */
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config->burstRead = false; /* Burst-Read disable */
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config->byteEnableMode = false; /* Byte-Enable mode is asserted for data write only */
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config->autoAcknowledge = true; /* Auto-Acknowledge enable */
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config->extendTransferAddress = false; /* Extend transfer start/extend address latch disable */
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config->secondaryWaitStatesEnable = false; /* Secondary wait state disable */
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config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */
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config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */
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config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */
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config->addressSetup =
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kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */
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config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */
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config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */
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config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */
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config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */
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config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */
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config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */
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} |