361 lines
18 KiB
C
361 lines
18 KiB
C
/*
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* The Clear BSD License
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* Copyright 2017-2018 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
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* and flash clock are in allowed range during clock mode switch.
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*
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* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
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*
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* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
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* internal reference clock(MCGIRCLK). Follow the steps to setup:
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*
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* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
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*
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* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
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* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
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* explicitly to setup MCGIRCLK.
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*
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* 3). Don't need to configure FLL explicitly, because if target mode is FLL
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* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
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* if the target mode is not FLL mode, the FLL is disabled.
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*
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* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
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* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
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* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
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*
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* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v4.1
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processor: MKS22FN256xxx12
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package_id: MKS22FN256VLL12
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mcu_data: ksdk2_0
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processor_version: 0.0.11
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "fsl_smc.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
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#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
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#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
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#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
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#define SIM_PLLFLLSEL_DIV_0 0U /*!< PLLFLLSEL clock divider divisor: divided by 1 */
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#define SIM_PLLFLLSEL_FRAC_0 0U /*!< PLLFLLSEL clock divider fraction: multiplied by 1 */
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#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
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#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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* Code
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******************************************************************************/
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetPllFllSelDivFrac
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* Description : Configure PLLFLLSEL divider divison and fraction in SIM
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* Param div : The value to set the divider division.
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* Param frac : The value to set the divider fraction.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetPllFllSelDivFrac(uint8_t div, uint8_t frac)
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{
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SIM->CLKDIV3 = ((SIM->CLKDIV3 & ~(SIM_CLKDIV3_PLLFLLDIV_MASK | SIM_CLKDIV3_PLLFLLFRAC_MASK))
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| SIM_CLKDIV3_PLLFLLDIV(div)
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| SIM_CLKDIV3_PLLFLLFRAC(frac));
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}
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/*FUNCTION**********************************************************************
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*
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* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
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* Description : Configure FLL external reference divider (FRDIV).
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* Param frdiv : The value to set FRDIV.
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*
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*END**************************************************************************/
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static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
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{
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MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
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}
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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/*******************************************************************************
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********************* Configuration BAORD_BootClockVLPR ***********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BAORD_BootClockVLPR
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outputs:
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- {id: Bus_clock.outFreq, value: 4 MHz}
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- {id: Core_clock.outFreq, value: 4 MHz}
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- {id: Flash_clock.outFreq, value: 800 kHz}
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- {id: LPO_clock.outFreq, value: 1 kHz}
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- {id: MCGIRCLK.outFreq, value: 4 MHz}
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- {id: System_clock.outFreq, value: 4 MHz}
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settings:
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- {id: MCGMode, value: BLPI}
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- {id: powerMode, value: VLPR}
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- {id: MCG.CLKS.sel, value: MCG.IRCS}
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- {id: MCG.FCRDIV.scale, value: '1', locked: true}
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- {id: MCG.FLL_mul.scale, value: '640', locked: true}
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- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
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- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
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- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
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- {id: RTCCLKOUTConfig, value: 'yes'}
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- {id: RTC_CR_OSCE_CFG, value: Enabled}
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- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC22PF}
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- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
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- {id: SIM.OUTDIV4.scale, value: '5', locked: true}
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- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
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sources:
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- {id: OSC.OSC.outFreq, value: 32.768 kHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BAORD_BootClockVLPR configuration
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******************************************************************************/
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const mcg_config_t mcgConfig_BAORD_BootClockVLPR =
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{
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.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
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.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
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.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
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.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
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.drs = kMCG_DrsLow, /* Low frequency range */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
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.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
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.pll0Config =
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{
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.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
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.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
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.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
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},
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};
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const sim_clock_config_t simConfig_BAORD_BootClockVLPR =
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{
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.pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
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.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
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.clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV4: /5 */
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};
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const osc_config_t oscConfig_BAORD_BootClockVLPR =
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{
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.freq = 0U, /* Oscillator frequency: 0Hz */
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.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
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.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
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.oscerConfig =
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{
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.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
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.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
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}
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};
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/*******************************************************************************
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* Code for BAORD_BootClockVLPR configuration
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******************************************************************************/
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void BAORD_BootClockVLPR(void)
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{
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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/* Set MCG to BLPI mode. */
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CLOCK_BootToBlpiMode(mcgConfig_BAORD_BootClockVLPR.fcrdiv,
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mcgConfig_BAORD_BootClockVLPR.ircs,
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mcgConfig_BAORD_BootClockVLPR.irclkEnableMode);
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BAORD_BootClockVLPR);
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/* Set the PLLFLLDIV and PLLFLLFRAC in SIM module. */
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CLOCK_CONFIG_SetPllFllSelDivFrac(SIM_PLLFLLSEL_DIV_0,
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SIM_PLLFLLSEL_FRAC_0);
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/* Set VLPR power mode. */
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SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
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#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
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SMC_SetPowerModeVlpr(SMC, false);
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#else
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SMC_SetPowerModeVlpr(SMC);
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#endif
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while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
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{
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}
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BAORD_BOOTCLOCKVLPR_CORE_CLOCK;
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: Bus_clock.outFreq, value: 36 MHz}
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- {id: Core_clock.outFreq, value: 72 MHz}
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- {id: Flash_clock.outFreq, value: 24 MHz}
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- {id: LPO_clock.outFreq, value: 1 kHz, locked: true, accuracy: '0.001'}
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- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
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- {id: OSCERCLK.outFreq, value: 8 MHz}
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- {id: OSCERCLK_UNDIV.outFreq, value: 8 MHz}
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- {id: PLLFLLCLK.outFreq, value: 72 MHz}
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- {id: System_clock.outFreq, value: 72 MHz}
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settings:
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- {id: MCGMode, value: PEE}
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- {id: MCG.FCRDIV.scale, value: '1', locked: true}
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- {id: MCG.FLL_mul.scale, value: '640', locked: true}
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- {id: MCG.FRDIV.scale, value: '32', locked: true}
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- {id: MCG.IREFS.sel, value: MCG.FRDIV}
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- {id: MCG.PLLS.sel, value: MCG.PLL}
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- {id: MCG.PRDIV.scale, value: '4', locked: true}
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- {id: MCG.VDIV.scale, value: '36', locked: true}
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- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
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- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
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- {id: MCG_C2_RANGE0_CFG, value: Very_high}
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- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
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- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
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- {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled}
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- {id: RTC_CR_OSCE_CFG, value: Enabled}
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- {id: SIM.CLKOUTSEL.sel, value: OSC.OSCERCLK}
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- {id: SIM.FLEXIOSRCSEL.sel, value: SIM.PLLFLLSEL}
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- {id: SIM.I2S0_DIVIDE.scale, value: '20', locked: true}
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- {id: SIM.I2S0_MOESEL.sel, value: SIM.I2S0_DIVIDE}
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- {id: SIM.LPI2C0SRCSEL.sel, value: SIM.PLLFLLDIV}
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- {id: SIM.LPI2C1SRCSEL.sel, value: SIM.PLLFLLDIV}
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- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLSEL}
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- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
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- {id: SIM.OUTDIV1.scale, value: '1', locked: true}
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- {id: SIM.OUTDIV2.scale, value: '2', locked: true}
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- {id: SIM.OUTDIV4.scale, value: '3', locked: true}
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- {id: SIM.PLLFLLDIV.scale, value: '1', locked: true}
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- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
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- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
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- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLDIV}
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- {id: SIM.TRACECLKSEL.sel, value: MCG.MCGOUTCLK}
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- {id: SIM.USBDIV.scale, value: '1', locked: true}
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- {id: SIM.USBFRAC.scale, value: '1', locked: true}
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sources:
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- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockRUN configuration
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******************************************************************************/
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const mcg_config_t mcgConfig_BOARD_BootClockRUN =
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{
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.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
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.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
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.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
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.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
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.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
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.drs = kMCG_DrsLow, /* Low frequency range */
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.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
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.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
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.pll0Config =
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{
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.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
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.prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
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.vdiv = 0xcU, /* VCO divider: multiplied by 36 */
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},
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};
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const sim_clock_config_t simConfig_BOARD_BootClockRUN =
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{
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.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
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.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
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.clkdiv1 = 0x1020000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV4: /3 */
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};
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const osc_config_t oscConfig_BOARD_BootClockRUN =
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{
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.freq = 8000000U, /* Oscillator frequency: 8000000Hz */
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.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
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.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
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.oscerConfig =
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{
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.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
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.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
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}
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};
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/*******************************************************************************
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* Code for BOARD_BootClockRUN configuration
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******************************************************************************/
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void BOARD_BootClockRUN(void)
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{
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/* Set the system clock dividers in SIM to safe value. */
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CLOCK_SetSimSafeDivs();
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/* Initializes OSC0 according to board configuration. */
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CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
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CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
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/* Configure the Internal Reference clock (MCGIRCLK). */
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CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
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mcgConfig_BOARD_BootClockRUN.ircs,
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mcgConfig_BOARD_BootClockRUN.fcrdiv);
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/* Configure FLL external reference divider (FRDIV). */
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CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
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/* Set MCG to PEE mode. */
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CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
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kMCG_PllClkSelPll0,
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&mcgConfig_BOARD_BootClockRUN.pll0Config);
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/* Set the clock configuration in SIM module. */
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CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
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/* Set the PLLFLLDIV and PLLFLLFRAC in SIM module. */
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CLOCK_CONFIG_SetPllFllSelDivFrac(SIM_PLLFLLSEL_DIV_0,
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SIM_PLLFLLSEL_FRAC_0);
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/* Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
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}
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