173 lines
9.8 KiB
C
173 lines
9.8 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Pins v3.0
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processor: MKS22FN256xxx12
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package_id: MKS22FN256VLL12
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mcu_data: ksdk2_0
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processor_version: 0.0.11
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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#include "fsl_common.h"
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#include "fsl_port.h"
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#include "pin_mux.h"
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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BOARD_InitPins:
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- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
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- pin_list:
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- {pin_num: '1', peripheral: UART1, signal: TX, pin_signal: ADC0_SE4a/PTE0/CLKOUT32K/SPI1_PCS1/UART1_TX/LPI2C1_SDA/RTC_CLKOUT}
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- {pin_num: '2', peripheral: UART1, signal: RX, pin_signal: ADC0_SE5a/PTE1/LLWU_P0/SPI1_SOUT/UART1_RX/LPI2C1_SCL/SPI1_SIN}
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- {pin_num: '53', peripheral: LPI2C0, signal: SCL, pin_signal: ADC0_SE8/PTB0/LLWU_P5/LPI2C0_SCL/TPM1_CH0/FXIO0_D4/UART0_RX, slew_rate: fast, open_drain: enable,
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drive_strength: low, pull_select: up, pull_enable: enable}
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- {pin_num: '54', peripheral: LPI2C0, signal: SDA, pin_signal: ADC0_SE9/PTB1/LPI2C0_SDA/TPM1_CH1/EWM_IN/FXIO0_D5/UART0_TX, slew_rate: fast, open_drain: enable,
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drive_strength: low, pull_select: up, pull_enable: enable}
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- {pin_num: '82', peripheral: LPI2C1, signal: SCL, pin_signal: PTC10/LPI2C1_SCL/I2S0_RX_FS/FXIO0_D2/I2S1_RX_FS, slew_rate: fast, open_drain: enable, pull_select: up,
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pull_enable: enable}
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- {pin_num: '83', peripheral: LPI2C1, signal: SDA, pin_signal: PTC11/LLWU_P11/LPI2C1_SDA/FXIO0_D3/I2S1_MCLK, slew_rate: fast, open_drain: enable, pull_select: up,
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pull_enable: enable}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitPins
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* Description : Configures pin routing and optionally pin electrical features.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitPins(void)
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{
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/* Port B Clock Gate Control: Clock enabled */
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CLOCK_EnableClock(kCLOCK_PortB);
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/* Port C Clock Gate Control: Clock enabled */
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CLOCK_EnableClock(kCLOCK_PortC);
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/* Port E Clock Gate Control: Clock enabled */
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CLOCK_EnableClock(kCLOCK_PortE);
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const port_pin_config_t portb0_pin53_config = {/* Internal pull-up resistor is enabled */
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kPORT_PullUp,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain is enabled */
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kPORT_OpenDrainEnable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Pin is configured as LPI2C0_SCL */
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kPORT_MuxAlt2,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORTB0 (pin 53) is configured as LPI2C0_SCL */
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PORT_SetPinConfig(PORTB, 0U, &portb0_pin53_config);
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const port_pin_config_t portb1_pin54_config = {/* Internal pull-up resistor is enabled */
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kPORT_PullUp,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain is enabled */
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kPORT_OpenDrainEnable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Pin is configured as LPI2C0_SDA */
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kPORT_MuxAlt2,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORTB1 (pin 54) is configured as LPI2C0_SDA */
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PORT_SetPinConfig(PORTB, 1U, &portb1_pin54_config);
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const port_pin_config_t portc10_pin82_config = {/* Internal pull-up resistor is enabled */
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kPORT_PullUp,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain is enabled */
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kPORT_OpenDrainEnable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Pin is configured as LPI2C1_SCL */
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kPORT_MuxAlt2,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORTC10 (pin 82) is configured as LPI2C1_SCL */
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PORT_SetPinConfig(PORTC, 10U, &portc10_pin82_config);
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const port_pin_config_t portc11_pin83_config = {/* Internal pull-up resistor is enabled */
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kPORT_PullUp,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain is enabled */
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kPORT_OpenDrainEnable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Pin is configured as LPI2C1_SDA */
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kPORT_MuxAlt2,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORTC11 (pin 83) is configured as LPI2C1_SDA */
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PORT_SetPinConfig(PORTC, 11U, &portc11_pin83_config);
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/* PORTE0 (pin 1) is configured as UART1_TX */
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PORT_SetPinMux(PORTE, 0U, kPORT_MuxAlt3);
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/* PORTE1 (pin 2) is configured as UART1_RX */
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PORT_SetPinMux(PORTE, 1U, kPORT_MuxAlt3);
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SIM->SOPT5 = ((SIM->SOPT5 &
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/* Mask bits to zero which are setting */
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(~(SIM_SOPT5_UART1TXSRC_MASK)))
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/* UART 1 transmit data source select: UART1_TX pin. */
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| SIM_SOPT5_UART1TXSRC(SOPT5_UART1TXSRC_UART_TX));
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}
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/***********************************************************************************************************************
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* EOF
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**********************************************************************************************************************/
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