669 lines
24 KiB
C
669 lines
24 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexio_i2s.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
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#endif
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/*******************************************************************************
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* Definitations
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******************************************************************************/
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enum _sai_transfer_state
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{
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kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */
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kFLEXIO_I2S_Idle, /*!< Transfer is done. */
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};
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Receive a piece of data in non-blocking way.
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*
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* @param base FLEXIO I2S base pointer
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* @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
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* @param buffer Pointer to the data to be read.
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* @param size Bytes to be read.
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*/
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static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size);
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/*!
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* @brief sends a piece of data in non-blocking way.
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*
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* @param base FLEXIO I2S base pointer
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* @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits.
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* @param buffer Pointer to the data to be written.
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* @param size Bytes to be written.
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*/
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static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
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{
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return FLEXIO_GetInstance(base->flexioBase);
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}
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static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
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{
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uint32_t i = 0;
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uint8_t j = 0;
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uint8_t bytesPerWord = bitWidth / 8U;
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uint32_t data = 0;
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uint32_t temp = 0;
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for (i = 0; i < size / bytesPerWord; i++)
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{
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for (j = 0; j < bytesPerWord; j++)
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{
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temp = (uint32_t)(*txData);
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data |= (temp << (8U * j));
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txData++;
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}
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base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth));
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data = 0;
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}
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}
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static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
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{
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uint32_t i = 0;
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uint8_t j = 0;
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uint8_t bytesPerWord = bitWidth / 8U;
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uint32_t data = 0;
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for (i = 0; i < size / bytesPerWord; i++)
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{
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data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex] >> (32U - bitWidth));
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for (j = 0; j < bytesPerWord; j++)
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{
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*rxData = (data >> (8U * j)) & 0xFF;
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rxData++;
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}
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}
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}
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void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config)
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{
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assert(base && config);
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flexio_shifter_config_t shifterConfig = {0};
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flexio_timer_config_t timerConfig = {0};
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate flexio clock. */
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CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Set shifter for I2S Tx data */
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shifterConfig.timerSelect = base->bclkTimerIndex;
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shifterConfig.pinSelect = base->txPinIndex;
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shifterConfig.timerPolarity = config->txTimerPolarity;
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutput;
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shifterConfig.pinPolarity = config->txPinPolarity;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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if (config->masterSlave == kFLEXIO_I2S_Master)
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{
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift;
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}
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else
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{
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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}
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FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig);
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/* Set shifter for I2S Rx Data */
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shifterConfig.timerSelect = base->bclkTimerIndex;
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shifterConfig.pinSelect = base->rxPinIndex;
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shifterConfig.timerPolarity = config->rxTimerPolarity;
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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shifterConfig.pinPolarity = config->rxPinPolarity;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig);
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/* Set Timer to I2S frame sync */
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if (config->masterSlave == kFLEXIO_I2S_Master)
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{
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
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timerConfig.pinSelect = base->fsPinIndex;
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timerConfig.pinPolarity = config->fsPinPolarity;
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timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
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timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
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timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
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}
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else
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{
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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timerConfig.pinSelect = base->fsPinIndex;
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timerConfig.pinPolarity = config->fsPinPolarity;
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timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge;
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timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
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timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
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}
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FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig);
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/* Set Timer to I2S bit clock */
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if (config->masterSlave == kFLEXIO_I2S_Master)
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{
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinSelect = base->bclkPinIndex;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutput;
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timerConfig.pinPolarity = config->bclkPinPolarity;
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timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableNever;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
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}
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else
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{
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinSelect = base->bclkPinIndex;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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timerConfig.pinPolarity = config->bclkPinPolarity;
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timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh;
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timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled;
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timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled;
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}
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FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig);
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/* If enable flexio I2S */
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if (config->enableI2S)
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{
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base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK;
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}
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else
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{
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base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK;
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}
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}
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void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config)
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{
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config->masterSlave = kFLEXIO_I2S_Master;
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config->enableI2S = true;
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config->txPinPolarity = kFLEXIO_PinActiveHigh;
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config->rxPinPolarity = kFLEXIO_PinActiveHigh;
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config->bclkPinPolarity = kFLEXIO_PinActiveHigh;
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config->fsPinPolarity = kFLEXIO_PinActiveLow;
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config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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}
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void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base)
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{
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base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0;
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base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0;
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base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0;
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base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0;
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base->flexioBase->TIMCFG[base->fsTimerIndex] = 0;
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base->flexioBase->TIMCMP[base->fsTimerIndex] = 0;
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base->flexioBase->TIMCTL[base->fsTimerIndex] = 0;
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base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0;
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base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0;
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base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0;
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}
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void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
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{
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if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
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{
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FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex);
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}
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if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable)
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{
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FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex);
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}
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}
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uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base)
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{
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uint32_t status = 0;
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status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->txShifterIndex)) >> base->txShifterIndex);
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status |=
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(((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)) >> (base->rxShifterIndex))
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<< 1U);
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return status;
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}
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void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask)
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{
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if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable)
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{
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FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex);
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}
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if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable)
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{
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FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex);
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}
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}
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void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz)
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{
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uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * 32U * 2U);
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uint32_t bclkDiv = 0;
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/* Shall keep bclk and fs div an integer */
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if (timDiv % 2)
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{
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timDiv += 1U;
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}
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/* Set Frame sync timer cmp */
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base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * timDiv - 1U);
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/* Set bit clock timer cmp */
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bclkDiv = ((timDiv / 2U - 1U) | (63U << 8U));
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base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv);
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}
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void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format)
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{
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/* Set Frame sync timer cmp */
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base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 4U - 3U);
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/* Set bit clock timer cmp */
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base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(32U * 2U - 1U);
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}
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void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size)
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{
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uint32_t i = 0;
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uint8_t bytesPerWord = bitWidth / 8U;
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for (i = 0; i < size / bytesPerWord; i++)
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{
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/* Wait until it can write data */
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while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0)
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{
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}
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FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord);
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txData += bytesPerWord;
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}
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/* Wait until the last data is sent */
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while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0)
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{
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}
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}
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void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size)
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{
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uint32_t i = 0;
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uint8_t bytesPerWord = bitWidth / 8U;
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for (i = 0; i < size / bytesPerWord; i++)
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{
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/* Wait until data is received */
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while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)))
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{
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}
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FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord);
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rxData += bytesPerWord;
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}
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}
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void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base,
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flexio_i2s_handle_t *handle,
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flexio_i2s_callback_t callback,
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void *userData)
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{
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assert(handle);
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IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
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/* Zero the handle. */
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memset(handle, 0, sizeof(*handle));
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/* Store callback and user data. */
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handle->callback = callback;
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handle->userData = userData;
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/* Save the context in global variables to support the double weak mechanism. */
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FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ);
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/* Set the TX/RX state. */
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handle->state = kFLEXIO_I2S_Idle;
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/* Enable interrupt in NVIC. */
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EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
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}
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void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base,
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flexio_i2s_handle_t *handle,
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flexio_i2s_callback_t callback,
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void *userData)
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{
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assert(handle);
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IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
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/* Zero the handle. */
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memset(handle, 0, sizeof(*handle));
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/* Store callback and user data. */
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handle->callback = callback;
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handle->userData = userData;
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/* Save the context in global variables to support the double weak mechanism. */
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FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ);
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/* Set the TX/RX state. */
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|
handle->state = kFLEXIO_I2S_Idle;
|
|
|
|
/* Enable interrupt in NVIC. */
|
|
EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]);
|
|
}
|
|
|
|
void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base,
|
|
flexio_i2s_handle_t *handle,
|
|
flexio_i2s_format_t *format,
|
|
uint32_t srcClock_Hz)
|
|
{
|
|
assert(handle && format);
|
|
|
|
/* Set the bitWidth to handle */
|
|
handle->bitWidth = format->bitWidth;
|
|
|
|
/* Set sample rate */
|
|
if (srcClock_Hz != 0)
|
|
{
|
|
/* It is master */
|
|
FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz);
|
|
}
|
|
else
|
|
{
|
|
FLEXIO_I2S_SlaveSetFormat(base, format);
|
|
}
|
|
}
|
|
|
|
status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base,
|
|
flexio_i2s_handle_t *handle,
|
|
flexio_i2s_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Check if the queue is full */
|
|
if (handle->queue[handle->queueUser].data)
|
|
{
|
|
return kStatus_FLEXIO_I2S_QueueFull;
|
|
}
|
|
if ((xfer->dataSize == 0) || (xfer->data == NULL))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Add into queue */
|
|
handle->queue[handle->queueUser].data = xfer->data;
|
|
handle->queue[handle->queueUser].dataSize = xfer->dataSize;
|
|
handle->transferSize[handle->queueUser] = xfer->dataSize;
|
|
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
|
|
|
|
/* Set the state to busy */
|
|
handle->state = kFLEXIO_I2S_Busy;
|
|
|
|
FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
|
|
|
|
/* Enable Tx transfer */
|
|
FLEXIO_I2S_Enable(base, true);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base,
|
|
flexio_i2s_handle_t *handle,
|
|
flexio_i2s_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Check if the queue is full */
|
|
if (handle->queue[handle->queueUser].data)
|
|
{
|
|
return kStatus_FLEXIO_I2S_QueueFull;
|
|
}
|
|
|
|
if ((xfer->dataSize == 0) || (xfer->data == NULL))
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
/* Add into queue */
|
|
handle->queue[handle->queueUser].data = xfer->data;
|
|
handle->queue[handle->queueUser].dataSize = xfer->dataSize;
|
|
handle->transferSize[handle->queueUser] = xfer->dataSize;
|
|
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
|
|
|
|
/* Set state to busy */
|
|
handle->state = kFLEXIO_I2S_Busy;
|
|
|
|
/* Enable interrupt */
|
|
FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
|
|
|
|
/* Enable Rx transfer */
|
|
FLEXIO_I2S_Enable(base, true);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Stop Tx transfer and disable interrupt */
|
|
FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable);
|
|
handle->state = kFLEXIO_I2S_Idle;
|
|
|
|
/* Clear the queue */
|
|
memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
|
|
handle->queueDriver = 0;
|
|
handle->queueUser = 0;
|
|
}
|
|
|
|
void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Stop rx transfer and disable interrupt */
|
|
FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable);
|
|
handle->state = kFLEXIO_I2S_Idle;
|
|
|
|
/* Clear the queue */
|
|
memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE);
|
|
handle->queueDriver = 0;
|
|
handle->queueUser = 0;
|
|
}
|
|
|
|
status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
|
|
status_t status = kStatus_Success;
|
|
|
|
if (handle->state != kFLEXIO_I2S_Busy)
|
|
{
|
|
status = kStatus_NoTransferInProgress;
|
|
}
|
|
else
|
|
{
|
|
*count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count)
|
|
{
|
|
assert(handle);
|
|
|
|
status_t status = kStatus_Success;
|
|
|
|
if (handle->state != kFLEXIO_I2S_Busy)
|
|
{
|
|
status = kStatus_NoTransferInProgress;
|
|
}
|
|
else
|
|
{
|
|
*count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize);
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle)
|
|
{
|
|
assert(i2sHandle);
|
|
|
|
flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
|
|
FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
|
|
uint8_t *buffer = handle->queue[handle->queueDriver].data;
|
|
uint8_t dataSize = handle->bitWidth / 8U;
|
|
|
|
/* Handle error */
|
|
if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex))
|
|
{
|
|
FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1U << base->txShifterIndex));
|
|
}
|
|
/* Handle transfer */
|
|
if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) != 0) &&
|
|
(handle->queue[handle->queueDriver].data != NULL))
|
|
{
|
|
FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize);
|
|
|
|
/* Update internal counter */
|
|
handle->queue[handle->queueDriver].dataSize -= dataSize;
|
|
handle->queue[handle->queueDriver].data += dataSize;
|
|
}
|
|
|
|
/* If finished a blcok, call the callback function */
|
|
if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
|
|
{
|
|
memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
|
|
handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
|
|
if (handle->callback)
|
|
{
|
|
(handle->callback)(base, handle, kStatus_Success, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If all data finished, just stop the transfer */
|
|
if (handle->queue[handle->queueDriver].data == NULL)
|
|
{
|
|
FLEXIO_I2S_TransferAbortSend(base, handle);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle)
|
|
{
|
|
assert(i2sHandle);
|
|
|
|
flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle;
|
|
FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase;
|
|
uint8_t *buffer = handle->queue[handle->queueDriver].data;
|
|
uint8_t dataSize = handle->bitWidth / 8U;
|
|
|
|
/* Handle transfer */
|
|
if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) &&
|
|
(handle->queue[handle->queueDriver].data != NULL))
|
|
{
|
|
FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize);
|
|
|
|
/* Update internal state */
|
|
handle->queue[handle->queueDriver].dataSize -= dataSize;
|
|
handle->queue[handle->queueDriver].data += dataSize;
|
|
}
|
|
|
|
/* If finished a blcok, call the callback function */
|
|
if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL))
|
|
{
|
|
memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t));
|
|
handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
|
|
if (handle->callback)
|
|
{
|
|
(handle->callback)(base, handle, kStatus_Success, handle->userData);
|
|
}
|
|
}
|
|
|
|
/* If all data finished, just stop the transfer */
|
|
if (handle->queue[handle->queueDriver].data == NULL)
|
|
{
|
|
FLEXIO_I2S_TransferAbortReceive(base, handle);
|
|
}
|
|
}
|