568 lines
21 KiB
C
568 lines
21 KiB
C
/*
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* The Clear BSD License
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* Copyright 2013-2016 Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted (subject to the limitations in the
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* disclaimer below) provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "fsl_ftfx_cache.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*!
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* @name Flash cache and speculation control defines
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* @{
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*/
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#if defined(MCM_PLACR_CFCC_MASK)
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#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1)
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#else
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#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0)
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#endif
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#define FLASH_CACHE_IS_CONTROLLED_BY_MSCM (0)
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#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK)
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#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1)
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#else
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#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0)
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#endif
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#if defined(MCM_PLACR_DFCS_MASK)
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#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1)
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#else
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#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0)
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#endif
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#if defined(MSCM_OCMDR_OCMC1_MASK) || defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR0_OCM1_MASK) || \
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defined(MSCM_OCMDR1_OCM1_MASK)
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#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1)
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#else
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#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0)
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#endif
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#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \
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defined(FMC_PFB01CR_S_B_INV_MASK)
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#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1)
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#else
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#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0)
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#endif
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM || FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC || \
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FLASH_CACHE_IS_CONTROLLED_BY_MCM || FLASH_CACHE_IS_CONTROLLED_BY_FMC || FLASH_CACHE_IS_CONTROLLED_BY_MSCM
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#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (1)
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#else
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#define FLASH_IS_CACHE_INVALIDATION_AVAILABLE (0)
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#endif
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/*@}*/
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/*! @brief A function pointer used to point to relocated ftfx_common_bit_operation() */
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typedef void (*callftfxCommonBitOperation_t)(FTFx_REG32_ACCESS_TYPE base,
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uint32_t bitMask,
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uint32_t bitShift,
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uint32_t bitValue);
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
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/*! @brief Performs the cache clear to the flash by MCM.*/
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void mcm_flash_cache_clear(ftfx_cache_config_t *config);
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#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
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#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM
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/*! @brief Performs the cache clear to the flash by MSCM.*/
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void mscm_flash_cache_clear(ftfx_cache_config_t *config);
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#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */
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#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
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/*! @brief Performs the cache clear to the flash by FMC.*/
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void fmc_flash_cache_clear(ftfx_cache_config_t *config);
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#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
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/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/
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void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable);
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#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
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/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
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void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config);
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#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
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#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
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/*! @brief Copy flash_cache_clear_command() to RAM*/
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static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation);
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#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
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/*!
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* @brief Position independent code of ftfx_common_bit_operation()
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*
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* Note1: The prototype of C function is shown as below:
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* @code
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* void ftfx_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t
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* bitValue)
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* {
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* if (bitMask)
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* {
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* uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask);
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* *base = (*base & (~bitMask)) | value;
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* }
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*
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* __ISB();
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* __DSB();
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* }
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* @endcode
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* Note2: The binary code is generated by IAR 7.70.1
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*/
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static const uint16_t s_ftfxCommonBitOperationFunctionCode[] = {
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0xb510, /* PUSH {R4, LR} */
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0x2900, /* CMP R1, #0 */
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0xd005, /* BEQ.N @12 */
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0x6804, /* LDR R4, [R0] */
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0x438c, /* BICS R4, R4, R1 */
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0x4093, /* LSLS R3, R3, R2 */
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0x4019, /* ANDS R1, R1, R3 */
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0x4321, /* ORRS R1, R1, R4 */
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0x6001, /* STR R1, [R0] */
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/* @12: */
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0xf3bf, 0x8f6f, /* ISB */
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0xf3bf, 0x8f4f, /* DSB */
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0xbd10 /* POP {R4, PC} */
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};
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#if (!FTFx_DRIVER_IS_EXPORTED)
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/*! @brief A static buffer used to hold ftfx_common_bit_operation() */
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static uint32_t s_ftfxCommonBitOperation[kFTFx_CACHE_RamFuncMaxSizeInWords];
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#endif /* (!FTFx_DRIVER_IS_EXPORTED) */
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#endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t FTFx_CACHE_Init(ftfx_cache_config_t *config)
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{
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if (config == NULL)
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{
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return kStatus_FTFx_InvalidArgument;
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}
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/* copy required flash commands to RAM */
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#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
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if (NULL == config->comBitOperFuncAddr)
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{
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#if FTFx_DRIVER_IS_EXPORTED
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return kStatus_FTFx_ExecuteInRamFunctionNotReady;
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#else
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config->comBitOperFuncAddr = s_ftfxCommonBitOperation;
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#endif /* FTFx_DRIVER_IS_EXPORTED */
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}
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ftfx_copy_common_bit_operation_to_ram(config->comBitOperFuncAddr);
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#endif /* FLASH_IS_CACHE_INVALIDATION_AVAILABLE && FTFx_DRIVER_IS_FLASH_RESIDENT */
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return kStatus_FTFx_Success;
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}
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/*!
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* @brief Flash Cache/Prefetch/Speculation Clear Process
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*
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* This function is used to perform the cache and prefetch speculation clear process to the flash.
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*/
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status_t FTFx_CACHE_ClearCachePrefetchSpeculation(ftfx_cache_config_t *config, bool isPreProcess)
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{
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/* We pass the ftfx register address as a parameter to ftfx_common_bit_operation() instead of using
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* pre-processed MACROs or a global variable in ftfx_common_bit_operation()
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* to make sure that ftfx_common_bit_operation() will be compiled into position-independent code (PIC). */
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if (!isPreProcess)
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{
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#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
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mcm_flash_cache_clear(config);
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#endif
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#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM
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mscm_flash_cache_clear(config);
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#endif
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#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
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fmc_flash_cache_clear(config);
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#endif
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
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mscm_flash_prefetch_speculation_enable(config, true);
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#endif
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
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fmc_flash_prefetch_speculation_clear(config);
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#endif
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}
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if (isPreProcess)
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{
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
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mscm_flash_prefetch_speculation_enable(config, false);
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#endif
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}
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return kStatus_FTFx_Success;
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}
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status_t FTFx_CACHE_PflashSetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus)
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{
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
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{
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if (speculationStatus->instructionOff)
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{
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if (!speculationStatus->dataOff)
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{
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return kStatus_FTFx_InvalidSpeculationOption;
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}
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else
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{
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MCM0_CACHE_REG |= MCM_PLACR_DFCS_MASK;
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}
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}
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else
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{
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MCM0_CACHE_REG &= ~MCM_PLACR_DFCS_MASK;
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if (!speculationStatus->dataOff)
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{
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MCM0_CACHE_REG |= MCM_PLACR_EFDS_MASK;
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}
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else
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{
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MCM0_CACHE_REG &= ~MCM_PLACR_EFDS_MASK;
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}
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}
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}
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#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
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{
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if (!speculationStatus->instructionOff)
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{
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FMC_CACHE_REG |= FMC_CACHE_B0IPE_MASK;
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}
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else
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{
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FMC_CACHE_REG &= ~FMC_CACHE_B0IPE_MASK;
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}
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if (!speculationStatus->dataOff)
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{
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FMC_CACHE_REG |= FMC_CACHE_B0DPE_MASK;
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}
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else
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{
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FMC_CACHE_REG &= ~FMC_CACHE_B0DPE_MASK;
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}
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/* Invalidate Prefetch Speculation Buffer */
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FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK;
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}
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#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
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{
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if (speculationStatus->instructionOff)
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{
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if (!speculationStatus->dataOff)
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{
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return kStatus_FTFx_InvalidSpeculationOption;
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}
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else
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{
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MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFCS_MASK;
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}
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}
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else
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{
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MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFCS_MASK;
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if (!speculationStatus->dataOff)
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{
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MSCM_OCMDR0_REG &= ~MSCM_OCMDR_OCMC1_DFDS_MASK;
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}
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else
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{
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MSCM_OCMDR0_REG |= MSCM_OCMDR_OCMC1_DFDS_MASK;
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}
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}
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}
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#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */
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return kStatus_FTFx_Success;
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}
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status_t FTFx_CACHE_PflashGetPrefetchSpeculation(ftfx_prefetch_speculation_status_t *speculationStatus)
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{
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memset(speculationStatus, 0, sizeof(ftfx_prefetch_speculation_status_t));
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/* Assuming that all speculation options are enabled. */
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speculationStatus->instructionOff = false;
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speculationStatus->dataOff = false;
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#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM
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{
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uint32_t value = MCM0_CACHE_REG;
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if (value & MCM_PLACR_DFCS_MASK)
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{
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/* Speculation buffer is off. */
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speculationStatus->instructionOff = true;
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speculationStatus->dataOff = true;
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}
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else
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{
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/* Speculation buffer is on for instruction. */
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if (!(value & MCM_PLACR_EFDS_MASK))
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{
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/* Speculation buffer is off for data. */
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speculationStatus->dataOff = true;
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}
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}
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}
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#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
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{
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uint32_t value = FMC_CACHE_REG;
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if (!(value & FMC_CACHE_B0DPE_MASK))
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{
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/* Do not prefetch in response to data references. */
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speculationStatus->dataOff = true;
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}
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if (!(value & FMC_CACHE_B0IPE_MASK))
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{
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/* Do not prefetch in response to instruction fetches. */
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speculationStatus->instructionOff = true;
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}
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}
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#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
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{
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uint32_t value = MSCM_OCMDR0_REG;
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if (value & MSCM_OCMDR_OCMC1_DFCS_MASK)
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{
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/* Speculation buffer is off. */
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speculationStatus->instructionOff = true;
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speculationStatus->dataOff = true;
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}
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else
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{
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/* Speculation buffer is on for instruction. */
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if (value & MSCM_OCMDR_OCMC1_DFDS_MASK)
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{
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/* Speculation buffer is off for data. */
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speculationStatus->dataOff = true;
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}
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}
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}
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#endif
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return kStatus_FTFx_Success;
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}
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#if FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE
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/*! @brief Copy PIC of ftfx_common_bit_operation() to RAM */
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static void ftfx_copy_common_bit_operation_to_ram(uint32_t *ftfxCommonBitOperation)
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{
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assert(sizeof(s_ftfxCommonBitOperationFunctionCode) <= (kFTFx_CACHE_RamFuncMaxSizeInWords * 4));
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memcpy(ftfxCommonBitOperation, s_ftfxCommonBitOperationFunctionCode,
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sizeof(s_ftfxCommonBitOperationFunctionCode));
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}
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#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT && FLASH_IS_CACHE_INVALIDATION_AVAILABLE */
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#if FLASH_CACHE_IS_CONTROLLED_BY_MCM
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/*! @brief Performs the cache clear to the flash by MCM.*/
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void mcm_flash_cache_clear(ftfx_cache_config_t *config)
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{
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FTFx_REG32_ACCESS_TYPE regBase;
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#if defined(MCM0_CACHE_REG)
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regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG;
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#elif defined(MCM1_CACHE_REG)
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regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG;
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#endif
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#if FTFx_DRIVER_IS_FLASH_RESIDENT
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/* Since the value of ARM function pointer is always odd, but the real start address
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* of function memory should be even, that's why +1 operation exist. */
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callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1);
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callftfxCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U);
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#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
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*regBase |= MCM_CACHE_CLEAR_MASK;
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/* Memory barriers for good measure.
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* All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
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__ISB();
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__DSB();
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#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
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}
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#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */
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#if FLASH_CACHE_IS_CONTROLLED_BY_MSCM
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/*! @brief Performs the cache clear to the flash by MSCM.*/
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void mscm_flash_cache_clear(ftfx_cache_config_t *config)
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{
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uint8_t setValue = 0x1U;
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/* The OCMDR[0] is always used to cache main Pflash*/
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/* For device with FlexNVM support, the OCMDR[1] is used to cache Dflash.
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* For device with secondary flash support, the OCMDR[1] is used to cache secondary Pflash. */
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#if FTFx_DRIVER_IS_FLASH_RESIDENT
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/* Since the value of ARM function pointer is always odd, but the real start address
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* of function memory should be even, that's why +1 operation exist. */
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callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1);
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switch (config->flashMemoryIndex)
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{
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case kFLASH_MemoryIndexSecondaryFlash:
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callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG, MSCM_CACHE_CLEAR_MASK,
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MSCM_CACHE_CLEAR_SHIFT, setValue);
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break;
|
|
case kFLASH_MemoryIndexPrimaryFlash:
|
|
default:
|
|
callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG, MSCM_CACHE_CLEAR_MASK,
|
|
MSCM_CACHE_CLEAR_SHIFT, setValue);
|
|
break;
|
|
}
|
|
#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
switch (config->flashMemoryIndex)
|
|
{
|
|
case kFLASH_MemoryIndexSecondaryFlash:
|
|
MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue);
|
|
/* Each cahce clear instaruction should be followed by below code*/
|
|
__ISB();
|
|
__DSB();
|
|
break;
|
|
case kFLASH_MemoryIndexPrimaryFlash:
|
|
default:
|
|
MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_CACHE_CLEAR_MASK)) | MSCM_CACHE_CLEAR(setValue);
|
|
/* Memory barriers for good measure.
|
|
* All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
|
|
__ISB();
|
|
__DSB();
|
|
break;
|
|
}
|
|
#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
}
|
|
#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MSCM */
|
|
|
|
#if FLASH_CACHE_IS_CONTROLLED_BY_FMC
|
|
/*! @brief Performs the cache clear to the flash by FMC.*/
|
|
void fmc_flash_cache_clear(ftfx_cache_config_t *config)
|
|
{
|
|
#if FTFx_DRIVER_IS_FLASH_RESIDENT
|
|
/* Since the value of ARM function pointer is always odd, but the real start address
|
|
* of function memory should be even, that's why +1 operation exist. */
|
|
callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1);
|
|
callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&FMC_CACHE_REG, FMC_CACHE_CLEAR_MASK, FMC_CACHE_CLEAR_SHIFT, 0xFU);
|
|
#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
FMC_CACHE_REG = (FMC_CACHE_REG & (~FMC_CACHE_CLEAR_MASK)) | FMC_CACHE_CLEAR(~0);
|
|
/* Memory barriers for good measure.
|
|
* All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
|
|
__ISB();
|
|
__DSB();
|
|
#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
}
|
|
#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */
|
|
|
|
#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM
|
|
/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/
|
|
void mscm_flash_prefetch_speculation_enable(ftfx_cache_config_t *config, bool enable)
|
|
{
|
|
uint8_t setValue;
|
|
if (enable)
|
|
{
|
|
setValue = 0x0U;
|
|
}
|
|
else
|
|
{
|
|
setValue = 0x3U;
|
|
}
|
|
|
|
/* The OCMDR[0] is always used to prefetch main Pflash*/
|
|
/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash.
|
|
* For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */
|
|
#if FTFx_DRIVER_IS_FLASH_RESIDENT
|
|
/* Since the value of ARM function pointer is always odd, but the real start address
|
|
* of function memory should be even, that's why +1 operation exist. */
|
|
callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1);
|
|
switch (config->flashMemoryIndex)
|
|
{
|
|
case 1:
|
|
callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR1_REG, MSCM_SPECULATION_SET_MASK,
|
|
MSCM_SPECULATION_SET_SHIFT, setValue);
|
|
break;
|
|
case 0:
|
|
default:
|
|
callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM_OCMDR0_REG, MSCM_SPECULATION_SET_MASK,
|
|
MSCM_SPECULATION_SET_SHIFT, setValue);
|
|
break;
|
|
}
|
|
#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
switch (config->flashMemoryIndex)
|
|
{
|
|
case kFLASH_MemoryIndexSecondaryFlash:
|
|
MSCM_OCMDR1_REG = (MSCM_OCMDR1_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue);
|
|
/* Each cahce clear instaruction should be followed by below code*/
|
|
__ISB();
|
|
__DSB();
|
|
break;
|
|
case kFLASH_MemoryIndexPrimaryFlash:
|
|
default:
|
|
MSCM_OCMDR0_REG = (MSCM_OCMDR0_REG & (~MSCM_SPECULATION_SET_MASK)) | MSCM_SPECULATION_SET(setValue);
|
|
/* Memory barriers for good measure.
|
|
* All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
|
|
__ISB();
|
|
__DSB();
|
|
break;
|
|
}
|
|
#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
}
|
|
#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */
|
|
|
|
#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC
|
|
/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/
|
|
void fmc_flash_prefetch_speculation_clear(ftfx_cache_config_t *config)
|
|
{
|
|
#if FTFx_DRIVER_IS_FLASH_RESIDENT
|
|
/* Since the value of ARM function pointer is always odd, but the real start address
|
|
* of function memory should be even, that's why +1 operation exist. */
|
|
callftfxCommonBitOperation_t callftfxCommonBitOperation = (callftfxCommonBitOperation_t)((uint32_t)config->comBitOperFuncAddr + 1);
|
|
callftfxCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&FMC_SPECULATION_INVALIDATE_REG, FMC_SPECULATION_INVALIDATE_MASK, FMC_SPECULATION_INVALIDATE_SHIFT, 1U);
|
|
#else /* !FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
FMC_SPECULATION_INVALIDATE_REG |= FMC_SPECULATION_INVALIDATE_MASK;
|
|
/* Memory barriers for good measure.
|
|
* All Cache, Branch predictor and TLB maintenance operations before this instruction complete */
|
|
__ISB();
|
|
__DSB();
|
|
#endif /* FTFx_DRIVER_IS_FLASH_RESIDENT */
|
|
}
|
|
#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */
|
|
|
|
|