240 lines
9.7 KiB
C
240 lines
9.7 KiB
C
/*
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** ###################################################################
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** Processors: MKS22FN128VFT12
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** MKS22FN128VLH12
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** MKS22FN128VLL12
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** MKS22FN256VFT12
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** MKS22FN256VLH12
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** MKS22FN256VLL12
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**
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** Compilers: Keil ARM C/C++ Compiler
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** Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** MCUXpresso Compiler
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**
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** Reference manual: KS22P100M120SF0RM, Rev. 3, May, 2016
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** Version: rev. 2.1, 2017-06-09
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** Build: b171226
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** The Clear BSD License
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted (subject to the limitations in the
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** disclaimer below) provided that the following conditions are met:
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**
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** * Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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**
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** * Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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**
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** * Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from
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** this software without specific prior written permission.
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**
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** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2015-06-23)
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** Initial version.
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** - rev. 2.0 (2015-10-10)
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** Update according to Rev1 RM, Sep 2015.
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** - rev. 2.1 (2017-06-09)
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** Update according to Rev3 RM, May 2016.
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**
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** ###################################################################
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*/
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/*!
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* @file MKS22F12
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* @version 2.1
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* @date 2017-06-09
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* @brief Device specific configuration file for MKS22F12 (implementation file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "fsl_device_registers.h"
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if (DISABLE_WDOG)
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/* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
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/* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
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WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
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/* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
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WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
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WDOG_STCTRLH_WAITEN_MASK |
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WDOG_STCTRLH_STOPEN_MASK |
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WDOG_STCTRLH_ALLOWUPDATE_MASK |
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WDOG_STCTRLH_CLKSRC_MASK |
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0x0100U;
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#endif /* (DISABLE_WDOG) */
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SystemInitHook();
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate (void) {
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uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
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uint16_t Divider;
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if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
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/* Output of FLL or PLL is selected */
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if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
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/* FLL is selected */
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if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
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/* External reference clock is selected */
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switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
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case 0x00U:
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MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
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break;
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case 0x01U:
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MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
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break;
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case 0x02U:
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default:
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MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
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break;
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}
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if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
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switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
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case 0x38U:
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Divider = 1536U;
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break;
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case 0x30U:
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Divider = 1280U;
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break;
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default:
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Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
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break;
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}
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} else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
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Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
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}
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MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
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} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
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MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
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} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
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/* Select correct multiplier to calculate the MCG output clock */
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switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
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case 0x00U:
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MCGOUTClock *= 640U;
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break;
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case 0x20U:
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MCGOUTClock *= 1280U;
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break;
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case 0x40U:
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MCGOUTClock *= 1920U;
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break;
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case 0x60U:
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MCGOUTClock *= 2560U;
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break;
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case 0x80U:
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MCGOUTClock *= 732U;
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break;
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case 0xA0U:
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MCGOUTClock *= 1464U;
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break;
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case 0xC0U:
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MCGOUTClock *= 2197U;
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break;
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case 0xE0U:
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MCGOUTClock *= 2929U;
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break;
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default:
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break;
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}
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} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
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/* PLL is selected */
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Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
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MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
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Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
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MCGOUTClock *= Divider; /* Calculate the MCG output clock */
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} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
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} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
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/* Internal reference clock is selected */
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if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
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MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
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} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
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Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
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MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
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} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
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} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
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/* External reference clock is selected */
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switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
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case 0x00U:
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MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
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break;
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case 0x01U:
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MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
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break;
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case 0x02U:
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default:
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MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
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break;
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}
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} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
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/* Reserved value */
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return;
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} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
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SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
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}
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/* ----------------------------------------------------------------------------
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-- SystemInitHook()
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---------------------------------------------------------------------------- */
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__attribute__ ((weak)) void SystemInitHook (void) {
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/* Void implementation of the weak function. */
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}
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