506 lines
14 KiB
C
506 lines
14 KiB
C
/*
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* Copyright 2022 MindMotion Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "hal_adc.h"
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void ADC_Init(ADC_Type * ADCx, ADC_Init_Type * init)
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{
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if (!init)
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{
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return;
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}
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ADCx->ADCFG = (ADCx->ADCFG & ~ADC_ADCFG_RSLTCTL_MASK)| ADC_ADCFG_RSLTCTL(init->Resolution);
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/* ADC conversion mode and conversion data result align. */
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ADCx->ADCR = (ADCx->ADCR & ~( ADC_ADCR_ADMD_MASK | ADC_ADCR_ALIGN_MASK) )
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| ADC_ADCR_ADMD(init->ConvMode)
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| ADC_ADCR_ALIGN(init->Align)
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;
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/* Set the single-end or diff conversion mode. */
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ADCx->ADCFG2 = ADCx->ADCFG2 & ~(ADC_ADCFG2_ADCSREF_MASK | ADC_ADCFG2_DC_MASK | ADC_ADCFG2_PSDC_MASK);
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if (ADC_SingleDiffConvMode_SingleEnd == init->SingleDiffMode)
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{
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ADCx->ADCFG2 |= ADC_ADCFG2_ADCSREF(init->SingleVolt);
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}
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else if (ADC_SingleDiffConvMode_Diff == init->SingleDiffMode)
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{
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ADCx->ADCFG2 |= ADC_ADCFG2_DC(init->DiffPair);
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}
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else if (ADC_SingleDiffConvMode_PseudoDiff == init->SingleDiffMode)
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{
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ADCx->ADCFG2 = ADCx->ADCFG2 | ( ADC_ADCFG2_DC(init->DiffPair) | ADC_ADCFG2_PSDC(init->DiffPair) );
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}
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}
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void ADC_Enable(ADC_Type * ADCx, bool enable)
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{
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if (enable)
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{
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ADCx->ADCFG |= ADC_ADCFG_ADEN_MASK;
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}
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else
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{
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ADCx->ADCFG &= ~ADC_ADCFG_ADEN_MASK;
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}
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}
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void ADC_EnableTempSensor(ADC_Type * ADCx, bool enable)
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{
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if (enable)
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{
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ADCx->ADCFG |= ADC_ADCFG_TSEN_MASK;
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}
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else
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{
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ADCx->ADCFG &= ~ADC_ADCFG_TSEN_MASK;
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}
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}
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/* Use VBG 1.2V as default voltage sensor. */
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void ADC_EnableVoltSensor(ADC_Type * ADCx, bool enable)
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{
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if (enable)
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{
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ADCx ->ADCFG |= ADC_ADCFG_VSEN_MASK;
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}
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else
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{
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ADCx->ADCFG &= ~ADC_ADCFG_VSEN_MASK;
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}
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}
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void ADC_EnableDMA(ADC_Type * ADCx, bool enable)
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{
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if (enable)
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{
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ADCx->ADCR |= ADC_ADCR_DMAEN_MASK;
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}
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else
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{
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ADCx->ADCR &= ~ADC_ADCR_DMAEN_MASK;
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}
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}
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void ADC_EnableInterrupts(ADC_Type * ADCx, uint32_t interrupts, bool enable)
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{
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if (enable)
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{
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if ( 0u != (ADC_INT_CONV_SLOT_DONE & interrupts) )
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{
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ADCx->ADCR |= ADC_ADCR_EOCIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_SAMPLE_DONE & interrupts) )
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{
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ADCx->ADCR |= ADC_ADCR_EOSMPIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_SEQ_DONE & interrupts) )
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{
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ADCx->ADCR |= ADC_ADCR_EOSIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_COMPARE_DONE & interrupts) )
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{
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ADCx->ADCR |= ADC_ADCR_AWDIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_CALIB_DONE & interrupts) )
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{
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ADCx->ANYCR |= ADC_ANYCR_EOCALIE_MASK;
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}
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if ( 0u != (ADC_INT_JCONV_SLOT_DONE & interrupts) )
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{
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ADCx->ANYCR |= ADC_ANYCR_JEOCIE_MASK;
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}
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if ( 0u != (ADC_INT_JCONV_SAMPLE_DONE & interrupts) )
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{
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ADCx->ANYCR |= ADC_ANYCR_JEOSMPIE_MASK;
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}
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if ( 0u != (ADC_INT_JCONV_SEQ_DONE & interrupts) )
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{
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ADCx->ANYCR |= ADC_ANYCR_JEOSIE_MASK;
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}
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}
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else
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{
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if ( 0u != (ADC_INT_CONV_SLOT_DONE & interrupts) )
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{
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ADCx->ADCR &= ~ADC_ADCR_EOCIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_SAMPLE_DONE & interrupts) )
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{
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ADCx->ADCR &= ~ADC_ADCR_EOSMPIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_SEQ_DONE & interrupts) )
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{
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ADCx->ADCR &= ~ADC_ADCR_EOSIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_COMPARE_DONE & interrupts) )
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{
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ADCx->ADCR &= ~ADC_ADCR_AWDIE_MASK;
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}
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if ( 0u != (ADC_INT_CONV_CALIB_DONE & interrupts) )
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{
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ADCx->ANYCR &= ~ ADC_ANYCR_EOCALIE_MASK;
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}
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if ( 0u != (ADC_INT_JCONV_SLOT_DONE & interrupts) )
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{
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ADCx->ANYCR &= ~ ADC_ANYCR_JEOCIE_MASK;
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}
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if ( 0u != (ADC_INT_JCONV_SAMPLE_DONE & interrupts) )
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{
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ADCx->ANYCR &= ~ ADC_ANYCR_JEOSMPIE_MASK;
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}
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if ( 0u != (ADC_INT_JCONV_SEQ_DONE & interrupts) )
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{
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ADCx->ANYCR &= ~ ADC_ANYCR_JEOSIE_MASK;
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}
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}
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}
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uint32_t ADC_GetStatus(ADC_Type * ADCx)
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{
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uint32_t flags = 0u;
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if ( 0u != (ADC_ADSTAEXT_EOCALIF_MASK & ADCx->ADSTAEXT) )
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{
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flags |= ADC_STATUS_CONV_CALIB_DONE;
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}
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if ( 0u != (ADC_ADSTAEXT_JEOCIF_MASK & ADCx->ADSTAEXT) )
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{
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flags |= ADC_STATUS_JCONV_SLOT_DONE;
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}
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if ( 0u != (ADC_ADSTAEXT_JEOSMPIF_MASK & ADCx->ADSTAEXT) )
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{
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flags |= ADC_STATUS_JCONV_SAMPLE_DONE;
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}
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if ( 0u != (ADC_ADSTAEXT_JEOSIF_MASK & ADCx->ADSTAEXT) )
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{
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flags |= ADC_STATUS_JCONV_SEQ_DONE;
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}
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if ( 0u != (ADC_ADSTAEXT_EOCIF_MASK & ADCx->ADSTAEXT) )
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{
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flags |= ADC_STATUS_CONV_SLOT_DONE;
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}
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if ( 0u != (ADC_ADSTAEXT_EOSMPIF_MASK & ADCx->ADSTAEXT) )
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{
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flags |= ADC_STATUS_CONV_SAMPLE_DONE;
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}
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if ( 0u != (ADC_ADSTA_EOSIF_MASK & ADCx->ADSTA) )
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{
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flags |= ADC_STATUS_CONV_SEQ_DONE;
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}
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if ( 0u != (ADC_ADSTA_AWDIF_MASK & ADCx->ADSTA) )
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{
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flags |= ADC_STATUS_CONV_COMPARE_DONE;
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}
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return flags;
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}
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void ADC_ClearStatus(ADC_Type * ADCx, uint32_t flags)
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{
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if ( 0u != (ADC_STATUS_CONV_CALIB_DONE & flags) )
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{
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ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCALIF_MASK;
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}
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if ( 0u != (ADC_STATUS_JCONV_SLOT_DONE & flags) )
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{
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ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOCIF_MASK;
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}
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if ( 0u != (ADC_STATUS_JCONV_SAMPLE_DONE & flags) )
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{
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ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOSMPIF_MASK;
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}
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if ( 0u != ( ADC_STATUS_JCONV_SEQ_DONE & flags) )
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{
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ADCx->ADSTAEXT = ADC_ADSTAEXT_JEOSIF_MASK;
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}
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if ( 0u != (ADC_STATUS_CONV_SLOT_DONE & flags) )
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{
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ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCIF_MASK;
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}
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if ( 0u != (ADC_STATUS_CONV_SAMPLE_DONE & flags) )
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{
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ADCx->ADSTAEXT = ADC_ADSTAEXT_EOSMPIF_MASK;
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}
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if ( 0u != (ADC_STATUS_CONV_SEQ_DONE & flags) )
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{
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ADCx->ADSTA = ADC_ADSTA_EOSIF_MASK;
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}
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if ( 0u != (ADC_STATUS_CONV_COMPARE_DONE & flags) )
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{
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ADCx->ADSTA = ADC_ADSTA_AWDIF_MASK;
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}
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}
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uint32_t ADC_GetConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags)
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{
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uint32_t tmp32 = ADCx->ADDATA;
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*channel = (tmp32 & (ADC_ADDATA_CHANNELSEL_MASK | ADC_ADDATA_CHANNELSELH_MASK) ) >> ADC_ADDATA_CHANNELSEL_SHIFT;
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if (flags)
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{
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*flags = (tmp32 & (ADC_ADDATA_OVERRUN_MASK | ADC_ADDATA_VALID_MASK) ) >> ADC_ADDATA_OVERRUN_SHIFT;
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}
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return (tmp32 & ADC_ADDATA_DATA_MASK ) >> ADC_ADDATA_DATA_SHIFT;
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}
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uint32_t ADC_GetSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags)
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{
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uint32_t tmp32 = ADCx ->ADDR[slot];
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if (flags)
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{
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*flags = (tmp32 & (ADC_ADDR_OVERRUN_MASK | ADC_ADDR_VALID_MASK) ) >> ADC_ADDR_OVERRUN_SHIFT;
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}
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return (tmp32 & ADC_ADDR_DATA_MASK ) >> ADC_ADDR_DATA_SHIFT;
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}
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uint32_t ADC_GetExtConvResult(ADC_Type * ADCx, uint32_t * channel, uint32_t * flags)
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{
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uint32_t tmp32 = ADCx->JADDATA;
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*channel = (tmp32 & ADC_JADDATA_JCHANNELSEL_MASK) >> ADC_JADDATA_JCHANNELSEL_SHIFT;
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if (flags)
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{
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*flags = (tmp32 & (ADC_JADDATA_JOVERRUN_MASK | ADC_JADDATA_JVALID_MASK) ) >> ADC_JADDATA_JOVERRUN_SHIFT;
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}
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return (tmp32 & ADC_JADDATA_JDATA_MASK ) >> ADC_JADDATA_JDATA_SHIFT;
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}
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uint32_t ADC_GetExtSlotConvResult(ADC_Type * ADCx, uint32_t slot, uint32_t * flags)
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{
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uint32_t tmp32 = ADCx ->JDR[slot];
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if (flags)
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{
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*flags = (tmp32 & (ADC_JDR_JOVERRUN_MASK | ADC_JDR_JVALID_MASK) ) >> ADC_JDR_JOVERRUN_SHIFT;
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}
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return (tmp32 & ADC_JDR_JDATA_MASK ) >> ADC_JDR_JDATA_SHIFT;
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}
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void ADC_SetChnSampleTime(ADC_Type * ADCx, uint32_t channel, ADC_SampleTime_Type sample_time)
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{
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if (channel < 8u)
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{
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ADCx->SMPR1 = (ADCx->SMPR1 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
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}
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else if (channel-8 < 8u)
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{
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channel-= 8u;
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ADCx->SMPR2 = (ADCx->SMPR2 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
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}
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else
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{
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channel-= 16u;
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ADCx->SMPR3 = (ADCx->SMPR3 & ~(0xF << (4u * channel))) | (sample_time << (4u * channel));
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}
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}
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void ADC_EnableHwTrigger(ADC_Type * ADCx, ADC_HwTriggerConf_Type * conf)
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{
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if ( !conf )
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{
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ADCx->ADCR &= ~ADC_ADCR_TRGEN_MASK;
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return;
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}
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/* Enable the hardware trigger. */
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ADCx->ADCR = ( ADCx->ADCR & ~( ADC_ADCR_TRGSHIFT_MASK | ADC_ADCR_TRGEDGE_MASK) )
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| ADC_ADCR_TRGEN_MASK
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| ADC_ADCR_TRGSHIFT(conf->DelayCycle)
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| ADC_ADCR_TRGEDGE(conf->Edge)
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;
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}
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void ADC_EnableSeqSlotFixed(ADC_Type * ADCx, uint32_t seq_slot, ADC_SeqFixedDirection_Type dir)
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{
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ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK;
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/* enable fixed channel. */
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ADCx->ADCHS = seq_slot;
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/* configure the scan direction. */
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ADCx->ADCR = (ADCx->ADCR & ~ADC_ADCR_SCANDIR_MASK)
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| ADC_ADCR_SCANDIR(dir)
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;
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}
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void ADC_EnableSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel)
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{
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if (slot_idx > 16u)
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{
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return; /* the available range of seq length is within 16u. */
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}
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/* enable any channel sequence mode. */
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ADCx->ANYCR |= ADC_ANYCR_CHANYMDEN_MASK;
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/* select the any slots number. */
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ADCx->ANYCFG = ADC_ANYCFG_CHANYNUM(slot_idx);
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uint32_t offset = slot_idx;
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/* fill the channel into each slot. */
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if (slot_idx < 8u)
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{
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ADCx->CHANY0 = (ADCx->CHANY0 & ~( 0xFF << (offset * 4u) )) | ( (channel & 0xF) << (offset * 4u) );
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}
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else
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{
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ADCx->CHANY1 = (ADCx->CHANY1 & ~( 0xFF << ((offset - 8u) * 4u) )) | ( (channel & 0xF) << ((offset - 8u) * 4u) );
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}
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ADCx->ANYCFG = (ADCx->ANYCFG & ~( 0x01 << (offset + 8u) )) | ( (channel >> 4 ) << (offset + 8u) );
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}
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void ADC_EnableExtSeqSlot(ADC_Type * ADCx, uint32_t slot_idx, uint32_t channel)
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{
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if (slot_idx > 4u)
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{
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return; /* the available range of seq length is within 4u. */
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}
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/* enable the inject channel sequence mode. */
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ADCx->ANYCR |= ADC_ANYCR_JCEN_MASK;
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/* select the inject slot number. */
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ADCx->JSQR = ADC_JSQR_JNUM(slot_idx);
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/* fill the channels into each slot of inject sequence. */
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uint32_t offset = slot_idx;
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ADCx->JSQR = (ADCx->JSQR &~(0x1F << (5u * offset)))| (channel & 0x1F) << (5u * offset);
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}
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void ADC_EnableAutoExtSeqSlot(ADC_Type * ADCx, bool enable)
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{
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if (enable)
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{
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ADCx->ANYCR |= ADC_ANYCR_JAUTO_MASK;
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}
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else
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{
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ADCx->ANYCR &= ~ADC_ANYCR_JAUTO_MASK;
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}
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}
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void ADC_DoExtSeqSlotSwTrigger(ADC_Type * ADCx, bool enable)
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{
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if (enable)
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{
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ADCx->ANYCR |= ADC_ANYCR_JADST_MASK;
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}
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else
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{
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ADCx->ANYCR &= ~ADC_ANYCR_JADST_MASK;
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}
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}
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void ADC_SetExtSlotCalibParam(ADC_Type * ADCx, uint32_t slot, uint32_t value)
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{
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ADCx->JOFR[slot] = ADC_JOFR_JOFFSET(value);
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}
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void ADC_DoSwTrigger(ADC_Type * ADCx, bool enable)
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{
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if (enable)
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{
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ADCx->ADCR |= ADC_ADCR_ADST_MASK;
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}
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else
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{
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ADCx->ADCR &= ~ADC_ADCR_ADST_MASK;
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}
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}
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void ADC_EnableHwComp(ADC_Type * ADCx, ADC_HwCompConf_Type * conf)
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{
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if ( !conf )
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{
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/* disable the hardware compare feature for both regular & any seq. */
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ADCx->ADCFG &= ~ADC_ADCFG_AWDEN_MASK;
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return;
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}
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/* enable the hardware compare feature. */
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ADCx->ADCFG |= ADC_ADCFG_AWDEN_MASK;
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/* setup the compare channel. */
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ADCx->ADCR = (ADCx->ADCR & ~(ADC_ADCR_CMPCHL_MASK | ADC_ADCR_CMPCHH_MASK))
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| ADC_ADCR_CMPCHL(0xf & conf->ChnNum)
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| ADC_ADCR_CMPCHH(conf->ChnNum >> 4)
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;
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/* setup the compare boundary. */
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ADCx->ADCMPR = ADC_ADCMPR_CMPLDATA(conf->LowLimit)
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| ADC_ADCMPR_CMPHDATA(conf->HighLimit)
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;
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}
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void ADC_DoAutoCalib(ADC_Type * ADCx)
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{
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ADCx->ANYCR |= ADC_ANYCR_ADCAL_MASK;
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while(0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_EOCALIF_MASK));
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/* clear the status. */
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ADCx->ADSTAEXT = ADC_ADSTAEXT_EOCALIF_MASK;
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}
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uint32_t ADC_GetCalibFactor(ADC_Type * ADCx, uint32_t * factor)
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{
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for (uint32_t i = 0; i < 17; i++)
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{
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ADCx->ADDATA = ADC_ADDATA_DATA((i + 1) << 9);
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factor[i]= ADCx->ADDATA & 0x1FF;
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while ( 0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_FREOCIF_MASK))
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{}
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ADCx->ADSTAEXT |= ADC_ADSTAEXT_FREOCIF_MASK;
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}
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return 1;
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}
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void ADC_SetCalibFactor(ADC_Type * ADCx, uint32_t * factor)
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{
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for (uint32_t i = 0; i < 17; i++)
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{
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ADCx->ADDATA = factor[i] | ( (i + 1) << 9);
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while ( 0u == (ADCx->ADSTAEXT & ADC_ADSTAEXT_FREOCIF_MASK))
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{}
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ADCx->ADSTAEXT |= ADC_ADSTAEXT_FREOCIF_MASK;
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}
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}
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void ADC_SetOverSample(ADC_Type * ADCx, ADC_OverSampleConf_Type *conf)
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{
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if (!conf)
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{
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return;
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}
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ADCx->ADCFG2 = ( ADCx->ADCFG2 & ~ (ADC_ADCFG2_ROVSE_MASK |ADC_ADCFG2_JOVSE_MASK | ADC_ADCFG2_OVSR_MASK | ADC_ADCFG2_OVSS_MASK | ADC_ADCFG2_TROVS_MASK) )
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| ADC_ADCFG2_OVSR(conf->Ratio)
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| ADC_ADCFG2_OVSS(conf->Div)
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| ADC_ADCFG2_TROVS(conf->Mode)
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|
| ADC_ADCFG2_JOVSE(conf->injectOverSampleMode)
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|
;
|
|
}
|
|
|
|
void ADC_ResetAllSlot(ADC_Type * ADCx)
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|
{
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|
/* wait for the latest conversion done. */
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|
while( (0u != (ADCx->ADSTA & ADC_ADSTA_BUSY_MASK)) | (0u != (ADCx->ADSTAEXT & ADC_ADSTAEXT_JBUSY_MASK)) )
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|
{}
|
|
/* disable the regular channel. */
|
|
ADCx->ADCHS = 0x00;
|
|
/* disable the any sequence. */
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|
ADCx->CHANY0 = 0x00;
|
|
ADCx->CHANY1 = 0x00;
|
|
/* reset the inject slot . */
|
|
ADCx->JSQR = 0x00;
|
|
/* disable inject conversion. */
|
|
ADCx->ANYCR &= ~ADC_ANYCR_JCEN_MASK;
|
|
/* disable sequence conversion. */
|
|
ADCx->ANYCR &= ~ADC_ANYCR_CHANYMDEN_MASK;
|
|
/* stop adc conversion. */
|
|
ADCx->ADCR |= ADC_ADCR_ADST_MASK;
|
|
}
|
|
/* EOF. */
|