464 lines
13 KiB
C
464 lines
13 KiB
C
/*
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* Copyright 2021 MindMotion Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "hal_tim.h"
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bool TIM_Init(TIM_Type * TIMx, TIM_Init_Type * init)
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{
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uint32_t cr1 = TIMx->CR1 &~ ( TIM_CR1_OPM_MASK
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| TIM_CR1_ARPE_MASK
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| TIM_CR1_CMS_MASK
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| TIM_CR1_DIR_MASK
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);
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cr1 |= TIM_CR1_OPM(init->PeriodMode);
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cr1 |= ((init->EnablePreloadPeriod) ? TIM_CR1_ARPE_MASK: 0u);
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/* Check the vadility of StepFreqHz. */
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if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) )
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{
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return false;
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}
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switch (init->CountMode)
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{
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case TIM_CountMode_Increasing:
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cr1 &= ~TIM_CR1_DIR_MASK;
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break;
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case TIM_CountMode_Decreasing:
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cr1 |= TIM_CR1_DIR_MASK;
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break;
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case TIM_CountMode_CenterAligned1:
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cr1 |= TIM_CR1_CMS(1u);
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break;
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case TIM_CountMode_CenterAligned2:
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cr1 |= TIM_CR1_CMS(2u);
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break;
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case TIM_CountMode_CenterAligned3:
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cr1 |= TIM_CR1_CMS(3u);
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break;
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default:
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break;
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}
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TIMx->CR1 = cr1;
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/* Calculate the prescaler. */
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TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u;
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TIMx->ARR = init->Period;
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return true;
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}
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void TIM_Start(TIM_Type * TIMx)
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{
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TIMx->CR1 |= TIM_CR1_CEN_MASK;
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}
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void TIM_Stop(TIM_Type * TIMx)
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{
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TIMx->CR1 &= ~TIM_CR1_CEN_MASK;
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}
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uint32_t TIM_GetCounterValue(TIM_Type * TIMx)
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{
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return TIMx->CNT;
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}
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void TIM_ClearCounterValue(TIM_Type * TIMx)
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{
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TIMx->CNT = 0u;
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}
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void TIM_EnableInterrupts(TIM_Type * TIMx, uint32_t interrupts, bool enable)
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{
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if (enable)
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{
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TIMx->DIER |= interrupts;
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}
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else
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{
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TIMx->DIER &= ~interrupts;
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}
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}
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void TIM_EnableDMA(TIM_Type * TIMx, uint32_t dmas, bool enable)
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{
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if (enable)
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{
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TIMx->DIER |= dmas;
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}
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else
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{
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TIMx->DIER &= ~dmas;
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}
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}
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void TIM_DoSwTrigger(TIM_Type * TIMx, uint32_t swtrgs)
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{
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TIMx->EGR = swtrgs;
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}
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uint32_t TIM_GetInterruptStatus(TIM_Type * TIMx)
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{
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return TIMx->SR;
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}
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void TIM_ClearInterruptStatus(TIM_Type * TIMx, uint32_t status)
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{
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TIMx->SR &= ~status;
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}
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/*******************************/
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static void _TIM_WriteChannelCtrlReg(TIM_Type * TIMx, uint32_t channel, uint32_t regval)
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{
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switch (channel)
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{
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case TIM_CHN_1:
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TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF)) | (regval & 0xFF);
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break;
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case TIM_CHN_2:
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TIMx->CCMR1 = (TIMx->CCMR1 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
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break;
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case TIM_CHN_3:
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TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF);
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break;
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case TIM_CHN_4:
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TIMx->CCMR2 = (TIMx->CCMR2 & ~(0xFF00)) | ((regval & 0xFF) << 8u);
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break;
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case TIM_CHN_5:
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TIMx->CCMR3 = (TIMx->CCMR2 & ~(0xFF)) | (regval & 0xFF);
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break;
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default:
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break;
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}
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}
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void TIM_EnableOutputCompare(TIM_Type * TIMx, uint32_t channel, TIM_OutputCompareConf_Type * conf)
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{
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uint32_t regval = TIM_CCMR1_CC1S(TIM_ChannelIOMode_Out) /* output compare mode. */
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| ( (conf->EnableFastOutput) ? TIM_CCMR1_OC1FE_MASK : 0u ) /* fast output. */
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| ( (conf->EnablePreLoadChannelValue) ? TIM_CCMR1_OC1PE_MASK : 0u) /* preload of channel value. */
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| TIM_CCMR1_OC1M(conf->RefOutMode) /* output compare comparison mode. */
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| ( (conf->ClearRefOutOnExtTrigger) ? TIM_CCMR1_OC1CE_MASK : 0u) /* external trigger clear ref. */
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;
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_TIM_WriteChannelCtrlReg(TIMx, channel, regval);
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TIM_PutChannelValue(TIMx, channel, conf->ChannelValue);
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switch (conf->PinPolarity)
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{
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case TIM_PinPolarity_Disabled:
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TIMx->CCER &= ~( ( TIM_CCER_CC1E_MASK
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| TIM_CCER_CC1NE_MASK
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) << (channel<<2u) ); /* Disable both channel. */
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break;
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case TIM_PinPolarity_Rising:
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TIMx->CCER = ( ( TIMx->CCER & ~(0xF << (channel<<2u)) )
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| ( ( TIM_CCER_CC1E_MASK ) /* Enable the pin output / input. */
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) << (channel<<2u));
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break;
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case TIM_PinPolarity_Falling:
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TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
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| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input. */
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| TIM_CCER_CC1P_MASK /* Set output active polarity. */
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) << (channel<<2u));
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break;
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default:
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break;
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}
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}
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void TIM_EnableCompOutput(TIM_Type * TIMx, uint32_t channel, bool enable)
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{
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if (enable)
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{
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switch (channel)
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{
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case TIM_CHN_1:
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TIMx->CCER |= TIM_CCER_CC1NE_MASK;
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break;
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case TIM_CHN_2:
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TIMx->CCER |= TIM_CCER_CC2NE_MASK;
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break;
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case TIM_CHN_3:
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TIMx->CCER |= TIM_CCER_CC3NE_MASK;
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break;
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case TIM_CHN_4:
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TIMx->CCER |= TIM_CCER_CC4NE_MASK;
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break;
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default:
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break;
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}
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}
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else
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{
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switch (channel)
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{
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case TIM_CHN_1:
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TIMx->CCER &= ~ TIM_CCER_CC1NE_MASK;
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break;
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case TIM_CHN_2:
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TIMx->CCER &= ~ TIM_CCER_CC2NE_MASK;
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break;
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case TIM_CHN_3:
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TIMx->CCER &= ~ TIM_CCER_CC3NE_MASK;
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break;
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case TIM_CHN_4:
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TIMx->CCER &= ~ TIM_CCER_CC4NE_MASK;
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break;
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default:
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break;
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}
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}
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}
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/* for some TIM instance, there is an additional switch to let the output signal go.
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* in this case, the output is disabled by default. then, only the switch is enabled, the output signal can go.
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*/
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void TIM_EnableOutputCompareSwitch(TIM_Type * TIMx, bool enable)
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{
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if (enable)
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{
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TIMx->BDTR |= TIM_BDTR_MOE_MASK;
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}
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else
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{
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TIMx->BDTR &= ~ TIM_BDTR_MOE_MASK;
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}
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}
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void TIM_EnableInputCapture(TIM_Type * TIMx, uint32_t channel, TIM_InputCaptureConf_Type * conf)
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{
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uint32_t regval = TIM_CCMR1_CC1S(TIM_ChannelIOMode_In) /* input capture mode. */
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| TIM_CCMR1_IC1PSC(conf->InDiv)
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| TIM_CCMR1_IC1F(conf->InFilter)
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;
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_TIM_WriteChannelCtrlReg(TIMx, channel, regval);
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switch (conf->PinPolarity)
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{
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case TIM_PinPolarity_Disabled:
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TIMx->CCER &= ~(TIM_CCER_CC1E_MASK << (channel<<2u));
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break;
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case TIM_PinPolarity_Rising:
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TIMx->CCER = (TIMx->CCER & ~(0xF << (channel<<2u)) )
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| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */
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) << (channel<<2u) );
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break;
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case TIM_PinPolarity_Falling:
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TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
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| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */
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| TIM_CCER_CC1P_MASK /* Set active input edge. */
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) << (channel<<2u) );
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break;
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case TIM_PinPolarity_RisingOrFalling:
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TIMx->CCER = ( TIMx->CCER & ~(0xF << (channel<<2u)) )
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| (( TIM_CCER_CC1E_MASK /* Enable the pin output / input */
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| TIM_CCER_CC1P_MASK /* Set active input edge. */
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| TIM_CCER_CC1NP_MASK
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) << (channel<<2u) );
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break;
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default:
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break;
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}
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}
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uint32_t TIM_GetChannelValue(TIM_Type * TIMx, uint32_t channel)
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{
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return TIMx->CCR[channel];
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}
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void TIM_PutChannelValue(TIM_Type * TIMx, uint32_t channel, uint32_t value)
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{
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if ( channel == TIM_CHN_5 )
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{
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TIMx->CCR5 = value;
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}
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else
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{
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TIMx->CCR[channel] = value;
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}
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}
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void TIM_SetClockDiv(TIM_Type * TIMx, TIM_ClockDiv_Type div)
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{
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TIMx->CR1 = ( TIMx->CR1 &~ TIM_CR1_CKD_MASK )
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| ( TIM_CR1_CKD(div) ); /* set the frequncy ratio. */
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}
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void TIM_EnableDeadPeriod(TIM_Type * TIMx, TIM_DeadPeriodConf_Type * conf)
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{
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TIMx->BDTR = ( TIMx->BDTR &~ TIM_BDTR_DTG_MASK )
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| ( TIM_BDTR_DTG(conf->DeadPeriodCoef) ); /* set the coefficient. */
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}
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void TIM_EnableMasterMode(TIM_Type * TIMx, TIM_MasterModeConf_Type * conf)
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{
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TIMx->CR2 = ( TIMx->CR2 &~ TIM_CR2_MMS_MASK )
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| ( TIM_CR2_MMS(conf->Out) ); /* Set master mode output. */
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uint32_t smcr = TIMx->SMCR &~ TIM_SMCR_MSM_MASK;
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if (conf->EnableSync) /* synchronize with slave timers. */
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{
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smcr |= TIM_SMCR_MSM_MASK;
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}
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TIMx->SMCR = smcr;
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}
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void TIM_EnableSlaveMode(TIM_Type * TIMx, TIM_SlaveModeConf_Type * conf)
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{
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if ( conf->Resp != TIM_SlaveResp_Disabled )
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{
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TIMx->SMCR = ( TIMx->SMCR &~ ( TIM_SMCR_TS_MASK
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| TIM_SMCR_SMS_MASK
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) )
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| TIM_SMCR_TS(conf->In) /* set input trigger source. */
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| TIM_SMCR_SMS(conf->Resp); /* set response to the source */
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}
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else
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{
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TIMx->SMCR &= ~ TIM_SMCR_SMS_MASK;
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}
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}
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void TIM_EnableExtTriggerIn(TIM_Type * TIMx, TIM_ExtTriggerInConf_Type * conf)
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{
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uint32_t smcr = TIMx->SMCR &~ ( TIM_SMCR_ETPS_MASK
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| TIM_SMCR_ETF_MASK
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| TIM_SMCR_ECE_MASK
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| TIM_SMCR_ETP_MASK
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);
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switch (conf->PinPolarity)
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{
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case TIM_PinPolarity_Disabled:
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break;
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case TIM_PinPolarity_Rising:
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smcr |= TIM_SMCR_ECE_MASK; /* enable external trigger input. */
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break;
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case TIM_PinPolarity_Falling:
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smcr |= TIM_SMCR_ETP_MASK; /* falling edge active. */
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smcr |= TIM_SMCR_ECE_MASK; /* enable external trigger input. */
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break;
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default:
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break;
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}
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smcr |= TIM_SMCR_ETPS( conf->InDiv ); /* division to the input external trigger. */
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smcr |= TIM_SMCR_ETF( conf->InFilter ); /* set filter. */
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TIMx->SMCR = smcr;
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}
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uint32_t TIM_EnableDMABurst(TIM_Type * TIMx, TIM_DMABurstConf_Type * conf)
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{
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TIMx->DCR = TIM_DCR_DBA(conf->BaseAddr) | TIM_DCR_DBL(conf->Length);
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return (uint32_t)(&(TIMx->DMAR));
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}
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TIM_EncoderDirection_Type TIM_GetEncoder(TIM_Type * TIMx, uint32_t * value)
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{
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if (value)
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{
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* value = TIM_GetCounterValue(TIMx);
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}
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if ( (TIMx->CR1 & TIM_CR1_DIR_MASK) != 0u )
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{
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return TIM_EncoderDirection_Backward;
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}
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else
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{
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return TIM_EncoderDirection_Forward;
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}
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}
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void TIM_SetRepCounter(TIM_Type * TIMx, uint8_t value)
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{
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TIMx->RCR = TIM_RCR_REP(value);
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}
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uint8_t TIM_GetRepCounterValue(TIM_Type * TIMx)
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{
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return TIMx->RCR >> TIM_RCR_REPCNT_SHIFT;
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}
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void TIM_EnableIdleOut(TIM_Type * TIMx, uint32_t channel, TIM_IdleOut_Type * conf)
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{
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uint32_t cr2 = TIMx->CR2 & ~ ( ( TIM_CR2_OIS1_MASK
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| TIM_CR2_OIS1N_MASK
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) << ( channel << 1u )
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);
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if ( conf->PinPolarity == TIM_PinPolarity_Rising )
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{
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cr2 |= ( TIM_CR2_OIS1_MASK << ( channel << 1u ) );
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}
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if ( conf->CompPinPolarity == TIM_PinPolarity_Rising )
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{
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cr2 |= ( TIM_CR2_OIS1N_MASK << ( channel << 1u ) );
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}
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TIMx->CR2 = cr2;
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}
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void TIM_EnableLock(TIM_Type * TIMx, TIM_LockLevel_Type lock)
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{
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TIMx->BDTR = ( TIMx->BDTR & ~ TIM_BDTR_LOCK_MASK )
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| TIM_BDTR_LOCK(lock);
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}
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void TIM_EnableBreakIn(TIM_Type * TIMx, TIM_BreakIn_Type * conf)
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{
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uint32_t bdtr = TIMx->BDTR &~ ( TIM_BDTR_BKE_MASK
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| TIM_BDTR_BKP_MASK
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| TIM_BDTR_AOE_MASK
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| TIM_BDTR_DOE_MASK
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);
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uint32_t bkinf = 0u;
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switch (conf->PinPolarity)
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{
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case TIM_PinPolarity_Disabled:
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break;
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case TIM_PinPolarity_Rising:
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bdtr |= ( TIM_BDTR_BKE_MASK
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| TIM_BDTR_BKP_MASK
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| ( conf->AutoSwitchOutput ? TIM_BDTR_AOE_MASK : 0u )
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| ( conf->DirectIdleOutput ? TIM_BDTR_DOE_MASK : 0u )
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);
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break;
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case TIM_PinPolarity_Falling:
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bdtr |= ( TIM_BDTR_BKE_MASK
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| ( conf->AutoSwitchOutput ? TIM_BDTR_AOE_MASK : 0u )
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| ( conf->DirectIdleOutput ? TIM_BDTR_DOE_MASK : 0u )
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);
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break;
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default:
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break;
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}
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if ( conf->Filter != TIM_BreakInFilter_Disabled )
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{
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bkinf |= ( TIM_BKINF_BKINFE_MASK | TIM_BKINF_BKINF(conf->Filter) );
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}
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bkinf |= conf->Source;
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TIMx->BKINF = bkinf;
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}
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void TIM_EnablePWMShift(TIM_Type * TIMx, uint32_t channel, TIM_PWMShift_Type * conf)
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{
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if ( NULL == conf )
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{
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TIMx->PDER &= ~( TIM_PDER_CCR1SHIFTEN_MASK << channel );
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}
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else
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{
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TIMx->PDER |= ( TIM_PDER_CCR1SHIFTEN_MASK << channel );
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TIMx->CCRFALL[channel] = conf->value;
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}
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}
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/* EOF. */
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