211 lines
6.3 KiB
C
211 lines
6.3 KiB
C
/*
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* Copyright 2021 MindMotion Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "hal_common.h"
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#include "clock_init.h"
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#include "hal_rcc.h"
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void CLOCK_ResetToDefault(void);
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void CLOCK_BootToHSI96MHz(void);
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void CLOCK_BootToHSE96MHz(void);
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void CLOCK_BootToHSE120MHz(void);
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void BOARD_InitBootClocks(void)
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{
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CLOCK_ResetToDefault();
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CLOCK_BootToHSE120MHz();
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/* UART1. */
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RCC_EnableAPB2Periphs(RCC_APB2_PERIPH_UART1, true);
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RCC_ResetAPB2Periphs(RCC_APB2_PERIPH_UART1);
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/* GPIOB. */
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RCC_EnableAHB1Periphs(RCC_AHB1_PERIPH_GPIOB, true);
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RCC_ResetAHB1Periphs(RCC_AHB1_PERIPH_GPIOB);
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/* SYSCFG. */
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RCC_EnableAPB2Periphs(RCC_APB2_PERIPH_SYSCFG, true);
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RCC_ResetAPB2Periphs(RCC_APB2_PERIPH_SYSCFG);
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}
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/* Switch to HSI. */
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void CLOCK_ResetToDefault(void)
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{
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/* Switch to HSI. */
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RCC->CR |= RCC_CR_HSION_MASK; /* Make sure the HSI is enabled. */
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while ( RCC_CR_HSIRDY_MASK != (RCC->CR & RCC_CR_HSIRDY_MASK) )
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{
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}
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RCC->CFGR = RCC_CFGR_SW(0u); /* Reset other clock sources and switch to HSI. */
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while ( RCC_CFGR_SWS(0u) != (RCC->CFGR & RCC_CFGR_SWS_MASK) ) /* Wait while the SYSCLK is switch to the HSI. */
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{
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}
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/* Reset all other clock sources. */
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RCC->CR = RCC_CR_HSION_MASK;
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/* Disable all interrupts and clear pending bits. */
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RCC->CIR = RCC->CIR; /* clear flags. */
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RCC->CIR = 0u; /* disable interrupts. */
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}
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/* Enable the PLL and use the HSI as input clock source. */
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void CLOCK_BootToHSI96MHz(void)
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{
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/* Increase the power to CPU core. */
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RCC->APB1ENR |= (1u << 28u); /* enable PWR/DBG. */
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PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS_MASK) | PWR_CR1_VOS(3u); /* 1.7V. */
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/* Setup PLL before enable it. */
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RCC->PLL1CFGR = RCC_PLL1CFGR_PLL1SRC(0) /* Use HSI as input source. */
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| RCC_PLL1CFGR_PLL1MUL(23) /* mul = 12, 24. */
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| RCC_PLL1CFGR_PLL1DIV(1) /* div = 2. */
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| RCC_PLL1CFGR_PLL1LDS(1) /* default. */
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| RCC_PLL1CFGR_PLL1ICTRL(3) /* default. */
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;
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/* Enable PLL. */
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RCC->CR |= RCC_CR_PLL1ON_MASK;
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while((RCC->CR & RCC_CR_PLL1RDY_MASK) == 0)
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{
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}
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/* Enable the FLASH prefetch. */
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RCC->AHB1ENR |= (1u << 13u); /* enable the access to FLASH. */
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FLASH->ACR = FLASH_ACR_LATENCY(3u) /* setup divider. */
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| FLASH_ACR_PRFTBE_MASK /* enable flash prefetch. */
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;
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/* Setup the dividers for each bus. */
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RCC->CFGR = RCC_CFGR_HPRE(0) /* div=1 for AHB freq. */
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| RCC_CFGR_PPRE1(0x4) /* div=2 for APB1 freq. */
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| RCC_CFGR_PPRE2(0x4) /* div=2 for APB2 freq. */
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| RCC_CFGR_USBPRE(1) /* div=2 for USB freq. */
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| RCC_CFGR_MCO(7) /* use PLL1 as output. */
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;
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/* Switch the system clock source to PLL. */
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW(2); /* Use PLL as SYSCLK */
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/* Wait till PLL is used as system clock source. */
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while ( (RCC->CFGR & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS(2) )
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{
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}
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}
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/*
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* After reset, the chip is running with the HSI (8MHz) clock with the divider equals 6.
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* The board is using 12MHz crystal for the OSC module.
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*/
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void CLOCK_BootToHSE96MHz(void)
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{
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RCC->APB1ENR |= (1u << 28u); /* enable PWR/DBG. */
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PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS_MASK) | PWR_CR1_VOS(3u); /* 1.7V. */
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/* enable HSE. */
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RCC->CR |= RCC_CR_HSEON_MASK;
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while ( RCC_CR_HSERDY_MASK != (RCC->CR & RCC_CR_HSERDY_MASK) )
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{
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}
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RCC->PLL1CFGR = RCC_PLL1CFGR_PLL1SRC(1)
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| RCC_PLL1CFGR_PLL1MUL(15)
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| RCC_PLL1CFGR_PLL1DIV(1)
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| RCC_PLL1CFGR_PLL1LDS(1)
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| RCC_PLL1CFGR_PLL1ICTRL(3)
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;
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/* Enable PLL. */
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RCC->CR |= RCC_CR_PLL1ON_MASK;
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while((RCC->CR & RCC_CR_PLL1RDY_MASK) == 0)
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{
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}
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/* Enable the FLASH prefetch. */
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RCC->AHB1ENR |= (1u << 13u); /* enable the access to FLASH. */
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FLASH->ACR = FLASH_ACR_LATENCY(3u) /* setup divider. */
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| FLASH_ACR_PRFTBE_MASK /* enable flash prefetch. */
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;
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/* Setup the dividers for each bus. */
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RCC->CFGR = RCC_CFGR_HPRE(0) /* div=1 for AHB freq. */
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| RCC_CFGR_PPRE1(0x4) /* div=2 for APB1 freq. */
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| RCC_CFGR_PPRE2(0x4) /* div=2 for APB2 freq. */
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| RCC_CFGR_USBPRE(1) /* div=2 for USB freq. */
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| RCC_CFGR_MCO(7) /* use PLL1 as output. */
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;
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/* Switch the system clock source to PLL. */
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW(2); /* Use PLL as SYSCLK */
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/* Wait till PLL is used as system clock source. */
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while ( (RCC->CFGR & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS(2) )
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{
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}
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}
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/* Enable the PLL and use the HSE as input clock source. */
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void CLOCK_BootToHSE120MHz(void)
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{
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RCC->APB1ENR |= (1u << 28u); /* enable PWR/DBG. */
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PWR->CR1 = (PWR->CR1 & ~PWR_CR1_VOS_MASK) | PWR_CR1_VOS(3u); /* 1.7V. */
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/* enable HSE. */
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RCC->CR |= RCC_CR_HSEON_MASK;
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while ( RCC_CR_HSERDY_MASK != (RCC->CR & RCC_CR_HSERDY_MASK) )
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{
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}
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RCC->PLL1CFGR = RCC_PLL1CFGR_PLL1SRC(1) /* (pllsrc == 1) ? HSE : HSI. */
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| RCC_PLL1CFGR_PLL1MUL(19) /* (12 * (19 + 1)) / 2 = 120. */
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| RCC_PLL1CFGR_PLL1DIV(1)
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| RCC_PLL1CFGR_PLL1LDS(1)
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| RCC_PLL1CFGR_PLL1ICTRL(3)
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;
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/* Enable PLL. */
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RCC->CR |= RCC_CR_PLL1ON_MASK;
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while((RCC->CR & RCC_CR_PLL1RDY_MASK) == 0)
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{
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}
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/* Enable the FLASH prefetch. */
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RCC->AHB1ENR |= (1u << 13u); /* enable the access to FLASH. */
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FLASH->ACR = FLASH_ACR_LATENCY(3u) /* setup divider. */
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| FLASH_ACR_PRFTBE_MASK /* enable flash prefetch. */
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;
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/* Setup the dividers for each bus. */
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RCC->CFGR = RCC_CFGR_HPRE(0) /* div=1 for AHB freq. */
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| RCC_CFGR_PPRE1(0x4) /* div=2 for APB1 freq. */
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| RCC_CFGR_PPRE2(0x4) /* div=2 for APB2 freq. */
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| RCC_CFGR_MCO(7) /* use PLL1 as output. */
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;
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/* Switch the system clock source to PLL. */
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW_MASK) | RCC_CFGR_SW(2); /* use PLL as SYSCLK */
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/* Wait till PLL is used as system clock source. */
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while ( (RCC->CFGR & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS(2) )
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{
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}
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}
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/* EOF. */
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