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Apply fixes to make life easier. 

Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun 2024-03-12 22:09:16 +08:00
parent 5dddc6e329
commit d18c9d0146
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
3 changed files with 267 additions and 114 deletions
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141
Ld/Link.ld
View File

@ -1 +1,140 @@
ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V30x_D8C - CH32V305RB-CH32V305FB CH32V30x_D8 - CH32V303CB-CH32V303RB */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ /* CH32V30x_D8C - CH32V307VC-CH32V307WC-CH32V307RC CH32V30x_D8 - CH32V303VC-CH32V303RC FLASH + RAM supports the following configuration FLASH-192K + RAM-128K FLASH-224K + RAM-96K FLASH-256K + RAM-64K FLASH-288K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM }
ENTRY( _start )
/* Configure heap and stack space reserved for application.
* Too low may cause standard library failed,
* too high may cause SRAM overflow.
* Collision may occur with heap when stack gets too deep.
*/
__stack_size = 2048;
__heap_size = 2048;
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
}
SECTIONS
{
.vectors :
{
. = ALIGN(4);
KEEP(*(SORT_NONE(.vectors)))
. = ALIGN(4);
} >FLASH
.text :
{
. = ALIGN(4);
_stext = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.rodata)
*(.rodata*)
*(.gnu.linkonce.r.*)
. = ALIGN(4);
_etext = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
.ctors :
{
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH
_sidata = LOADADDR(.data);
.data :
{
. = ALIGN(4);
_sdata = .;
*(.data .data.*)
*(.gnu.linkonce.d.*)
*(.sdata .sdata.*)
*(.srodata .srodata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(4);
_edata = .;
} >RAM AT>FLASH
. = ALIGN(16);
PROVIDE( __global_pointer$ = . );
.bss :
{
. = ALIGN(4);
_sbss = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} >RAM
.heap_stack :
{
. = ALIGN(8);
_end = .;
PROVIDE(end = . );
. = . + __heap_size;
. = ALIGN(8);
PROVIDE(_heap_end = .);
. = . + __stack_size;
. = ALIGN(8);
} >RAM
/* Place initial SP to the end of SRAM */
__stack_top = ORIGIN(RAM) + LENGTH(RAM);
PROVIDE(_eusrstack = __stack_top);
}

119
Startup/startup_ch32v30x_D8.S
View File

@ -10,16 +10,16 @@
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
.section .init,"ax",@progbits
.global _start
.align 1
.section .vectors,"ax",@progbits
.global _start
.align 4
_start:
j handle_reset
j Reset_Handler /* Go! */
.section .vector,"ax",@progbits
.align 1
_vector_base:
.option norvc;
.align 8
.option push
.option norvc
_vectors:
.word _start
.word 0
.word NMI_Handler /* NMI */
@ -126,8 +126,9 @@ _vector_base:
.word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
.word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
.option rvc;
.section .text.vector_handler, "ax", @progbits
.option pop;
.section .text.vector_handler, "ax", @progbits
.weak NMI_Handler /* NMI */
.weak HardFault_Handler /* Hard Fault */
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
@ -300,57 +301,63 @@ DMA2_Channel11_IRQHandler:
1:
j 1b
.section .text.handle_reset,"ax",@progbits
.weak handle_reset
.align 1
handle_reset:
.section .text,"ax",@progbits
Reset_Handler:
.option push
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/* Configure pipelining and instruction prediction */
.option norelax
la gp, __global_pointer$
.option pop
la sp, _eusrstack
copy_data:
/* Load data section from flash to RAM */
la a0, _sidata
la a1, _sdata
la a2, _edata
bgeu a1, a2, clear_bss
loop_copy_data:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, loop_copy_data
clear_bss:
/* Clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, setup_interrupts
loop_clear_bss:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, loop_clear_bss
setup_interrupts:
li t0, 0x1f
csrw 0xbc0, t0
/* Enable interrupt nesting and hardware stack */
li t0, 0x0b
csrw 0x804, t0
/* Enable floating point and global interrupt, configure privileged mode */
li t0, 0x6088
csrw mstatus, t0
/* Configure the interrupt vector table recognition mode and entry address mode */
la t0, _vector_base
ori t0, t0, 3
csrw mtvec, t0
jal SystemInit
la t0, main
csrw mepc, t0
mret
/* For MRS proprietary GCC compilers only: */
/* -- Enable nested and hardware stack */
/* li t0, 0x1f */
/* Enable nested interrupt, disable hardware stack */
li t0, 0x1e /* Refer to RISC-V4 PFIC manual */
csrw 0x804, t0
/* FS: Initial, MPP: M mode, MPIE: EN, MIE: EN */
li t0, 0x3888
csrs mstatus, t0
la t0, _vectors
ori t0, t0, 3 /* PFIC exception handling */
csrw mtvec, t0
jal SystemInit
jal main
dead_loop:
j dead_loop

121
Startup/startup_ch32v30x_D8C.S
View File

@ -10,16 +10,16 @@
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
.section .init,"ax",@progbits
.global _start
.align 1
.section .vectors,"ax",@progbits
.global _start
.align 4
_start:
j handle_reset
j Reset_Handler /* Go! */
.section .vector,"ax",@progbits
.align 1
_vector_base:
.option norvc;
.align 8
.option push
.option norvc
_vectors:
.word _start
.word 0
.word NMI_Handler /* NMI */
@ -126,8 +126,9 @@ _vector_base:
.word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
.word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
.option rvc;
.section .text.vector_handler, "ax", @progbits
.option pop;
.section .text.vector_handler, "ax", @progbits
.weak NMI_Handler /* NMI */
.weak HardFault_Handler /* Hard Fault */
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
@ -320,55 +321,61 @@ DMA2_Channel11_IRQHandler:
1:
j 1b
.section .text.handle_reset,"ax",@progbits
.weak handle_reset
.align 1
handle_reset:
.option push
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/* Configure pipelining and instruction prediction */
.section .text,"ax",@progbits
Reset_Handler:
.option push
.option norelax
la gp, __global_pointer$
.option pop
la sp, _eusrstack
copy_data:
/* Load data section from flash to RAM */
la a0, _sidata
la a1, _sdata
la a2, _edata
bgeu a1, a2, clear_bss
loop_copy_data:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, loop_copy_data
clear_bss:
/* Clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, setup_interrupts
loop_clear_bss:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, loop_clear_bss
setup_interrupts:
li t0, 0x1f
csrw 0xbc0, t0
/* Enable interrupt nesting and hardware stack */
li t0, 0x0b
csrw 0x804, t0
/* Enable floating point and global interrupt, configure privileged mode */
li t0, 0x6088
csrw mstatus, t0
/* Configure the interrupt vector table recognition mode and entry address mode */
la t0, _vector_base
ori t0, t0, 3
csrw mtvec, t0
jal SystemInit
la t0, main
csrw mepc, t0
mret
/* Enable nested and hardware stack */
/* li t0, 0x1f */ /* For MRS proprietary GCC compilers */
/* Enable nested interrupt, disable hardware stack */
li t0, 0x1e /* Refer to RISC-V4 PFIC manual */
csrw 0x804, t0
/* FS: Initial, MPP: M mode, MPIE: EN, MIE: EN */
li t0, 0x3888
csrs mstatus, t0
la t0, _vectors
ori t0, t0, 3 /* PFIC exception handling */
csrw mtvec, t0
jal SystemInit
jal main
dead_loop:
j dead_loop