598 lines
18 KiB
C
598 lines
18 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : core_riscv.h
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* Author : WCH
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* Version : V1.0.1
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* Date : 2024/03/06
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* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V30x
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#ifndef __CORE_RISCV_H__
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#define __CORE_RISCV_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* IO definitions */
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#ifdef __cplusplus
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#define __I volatile /* defines 'read only' permissions */
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#else
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#define __I volatile const /* defines 'read only' permissions */
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#endif
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#define __O volatile /* defines 'write only' permissions */
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#define __IO volatile /* defines 'read / write' permissions */
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/* Standard Peripheral Library old types (maintained for legacy purpose) */
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typedef __I uint64_t vuc64; /* Read Only */
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typedef __I uint32_t vuc32; /* Read Only */
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typedef __I uint16_t vuc16; /* Read Only */
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typedef __I uint8_t vuc8; /* Read Only */
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typedef const uint64_t uc64; /* Read Only */
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typedef const uint32_t uc32; /* Read Only */
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typedef const uint16_t uc16; /* Read Only */
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typedef const uint8_t uc8; /* Read Only */
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typedef __I int64_t vsc64; /* Read Only */
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typedef __I int32_t vsc32; /* Read Only */
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typedef __I int16_t vsc16; /* Read Only */
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typedef __I int8_t vsc8; /* Read Only */
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typedef const int64_t sc64; /* Read Only */
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typedef const int32_t sc32; /* Read Only */
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typedef const int16_t sc16; /* Read Only */
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typedef const int8_t sc8; /* Read Only */
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typedef __IO uint64_t vu64;
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typedef __IO uint32_t vu32;
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typedef __IO uint16_t vu16;
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typedef __IO uint8_t vu8;
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef __IO int64_t vs64;
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typedef __IO int32_t vs32;
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typedef __IO int16_t vs16;
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typedef __IO int8_t vs8;
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typedef int64_t s64;
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
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#define RV_STATIC_INLINE static inline
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/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
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typedef struct{
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__I uint32_t ISR[8];
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__I uint32_t IPR[8];
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__IO uint32_t ITHRESDR;
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__IO uint32_t RESERVED;
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__IO uint32_t CFGR;
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__I uint32_t GISR;
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__IO uint8_t VTFIDR[4];
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uint8_t RESERVED0[12];
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__IO uint32_t VTFADDR[4];
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uint8_t RESERVED1[0x90];
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__O uint32_t IENR[8];
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uint8_t RESERVED2[0x60];
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__O uint32_t IRER[8];
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uint8_t RESERVED3[0x60];
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__O uint32_t IPSR[8];
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uint8_t RESERVED4[0x60];
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__O uint32_t IPRR[8];
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uint8_t RESERVED5[0x60];
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__IO uint32_t IACTR[8];
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uint8_t RESERVED6[0xE0];
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__IO uint8_t IPRIOR[256];
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uint8_t RESERVED7[0x810];
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__IO uint32_t SCTLR;
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}PFIC_Type;
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/* memory mapped structure for SysTick */
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typedef struct
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{
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__IO uint32_t CTLR;
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__IO uint32_t SR;
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__IO uint64_t CNT;
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__IO uint64_t CMP;
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}SysTick_Type;
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#define PFIC ((PFIC_Type *) 0xE000E000 )
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#define NVIC PFIC
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#define NVIC_KEY1 ((uint32_t)0xFA050000)
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#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
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#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
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#define SysTick ((SysTick_Type *) 0xE000F000)
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/*********************************************************************
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* @fn __enable_irq
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*
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* @brief Enable Global Interrupt
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
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{
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__asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
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}
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/*********************************************************************
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* @fn __disable_irq
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*
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* @brief Disable Global Interrupt
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
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{
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__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
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}
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/*********************************************************************
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* @fn __NOP
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*
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* @brief nop
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
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{
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__asm volatile ("nop");
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}
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/*********************************************************************
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* @fn NVIC_EnableIRQ
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*
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* @brief Enable Interrupt
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_DisableIRQ
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*
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* @brief Disable Interrupt
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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{
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NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_GetStatusIRQ
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*
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* @brief Get Interrupt Enable State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1 - Interrupt Enable
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* 0 - Interrupt Disable
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
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{
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return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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}
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/*********************************************************************
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* @fn NVIC_GetPendingIRQ
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*
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* @brief Get Interrupt Pending State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1 - Interrupt Pending Enable
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* 0 - Interrupt Pending Disable
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
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{
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return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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}
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/*********************************************************************
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* @fn NVIC_SetPendingIRQ
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*
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* @brief Set Interrupt Pending
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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{
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NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_ClearPendingIRQ
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*
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* @brief Clear Interrupt Pending
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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{
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NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_GetActive
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*
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* @brief Get Interrupt Active State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1 - Interrupt Active
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* 0 - Interrupt No Active
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
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{
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return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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}
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/*********************************************************************
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* @fn NVIC_SetPriority
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*
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* @brief Set Interrupt Priority
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*
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* @param IRQn - Interrupt Numbers
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* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
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* priority - bit[7:5] - Preemption Priority
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* bit[4:0] - Reserve
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* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
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* priority - bit[7:6] - Preemption Priority
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* bit[5] - Sub priority
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* bit[4:0] - Reserve
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* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
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* priority - bit[7] - Preemption Priority
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* bit[6:5] - Sub priority
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* bit[4:0] - Reserve
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* interrupt nesting disable(CSR-0x804 bit1 = 0)
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* priority - bit[7:5] - Sub priority
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* bit[4:0] - Reserve
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
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{
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NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
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}
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/*********************************************************************
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* @fn __WFI
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*
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* @brief Wait for Interrupt
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
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{
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NVIC->SCTLR &= ~(1<<3); // wfi
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asm volatile ("wfi");
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}
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/*********************************************************************
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* @fn _SEV
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*
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* @brief Set Event
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
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{
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uint32_t t;
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t = NVIC->SCTLR;
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NVIC->SCTLR |= (1<<3)|(1<<5);
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NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
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}
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/*********************************************************************
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* @fn _WFE
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*
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* @brief Wait for Events
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
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{
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NVIC->SCTLR |= (1<<3);
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asm volatile ("wfi");
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}
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/*********************************************************************
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* @fn __WFE
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*
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* @brief Wait for Events
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
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{
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_SEV();
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_WFE();
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_WFE();
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}
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/*********************************************************************
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* @fn SetVTFIRQ
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*
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* @brief Set VTF Interrupt
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*
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* @param add - VTF interrupt service function base address.
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* IRQn -Interrupt Numbers
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* num - VTF Interrupt Numbers
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* NewState - DISABLE or ENABLE
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
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{
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if(num > 3) return ;
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if (NewState != DISABLE)
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{
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NVIC->VTFIDR[num] = IRQn;
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NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
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}
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else
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{
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NVIC->VTFIDR[num] = IRQn;
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NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
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}
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}
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/*********************************************************************
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* @fn NVIC_SystemReset
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*
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* @brief Initiate a system reset request
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
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{
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NVIC->CFGR = NVIC_KEY3|(1<<7);
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}
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/*********************************************************************
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* @fn __AMOADD_W
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*
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* @brief Atomic Add with 32bit value
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* Atomically ADD 32bit value with value in memory using amoadd.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be ADDed
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*
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* @return return memory value + add value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
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{
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int32_t result;
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__asm volatile ("amoadd.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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}
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/*********************************************************************
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* @fn __AMOAND_W
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*
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* @brief Atomic And with 32bit value
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* Atomically AND 32bit value with value in memory using amoand.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be ANDed
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*
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* @return return memory value & and value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
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{
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int32_t result;
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__asm volatile ("amoand.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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}
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/*********************************************************************
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* @fn __AMOMAX_W
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*
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* @brief Atomic signed MAX with 32bit value
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* Atomically signed max compare 32bit value with value in memory using amomax.d.
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be compared
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*
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* @return return the bigger value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
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{
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int32_t result;
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__asm volatile ("amomax.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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}
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/*********************************************************************
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* @fn __AMOMAXU_W
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*
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* @brief Atomic unsigned MAX with 32bit value
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* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be compared
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*
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* @return return the bigger value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
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{
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uint32_t result;
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__asm volatile ("amomaxu.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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}
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/*********************************************************************
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* @fn __AMOMIN_W
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*
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* @brief Atomic signed MIN with 32bit value
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* Atomically signed min compare 32bit value with value in memory using amomin.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be compared
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*
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* @return return the smaller value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
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{
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int32_t result;
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__asm volatile ("amomin.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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}
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/*********************************************************************
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* @fn __AMOMINU_W
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*
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* @brief Atomic unsigned MIN with 32bit value
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* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be compared
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*
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* @return return the smaller value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
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{
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uint32_t result;
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__asm volatile ("amominu.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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}
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/*********************************************************************
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* @fn __AMOOR_W
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*
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* @brief Atomic OR with 32bit value
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* Atomically OR 32bit value with value in memory using amoor.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be ORed
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*
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* @return return memory value | and value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
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{
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int32_t result;
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__asm volatile ("amoor.w %0, %2, %1" : \
|
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
|
return *addr;
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __AMOSWAP_W
|
|
*
|
|
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
|
*
|
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
|
* newval - New value to be stored into the address
|
|
*
|
|
* @return return the original value in memory
|
|
*/
|
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
|
{
|
|
uint32_t result;
|
|
|
|
__asm volatile ("amoswap.w %0, %2, %1" : \
|
|
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
|
return result;
|
|
}
|
|
|
|
/*********************************************************************
|
|
* @fn __AMOXOR_W
|
|
*
|
|
* @brief Atomic XOR with 32bit value
|
|
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
|
*
|
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
|
* value - value to be XORed
|
|
*
|
|
* @return return memory value ^ and value
|
|
*/
|
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
|
{
|
|
int32_t result;
|
|
|
|
__asm volatile ("amoxor.w %0, %2, %1" : \
|
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
|
return *addr;
|
|
}
|
|
|
|
/* Core_Exported_Functions */
|
|
extern uint32_t __get_FFLAGS(void);
|
|
extern void __set_FFLAGS(uint32_t value);
|
|
extern uint32_t __get_FRM(void);
|
|
extern void __set_FRM(uint32_t value);
|
|
extern uint32_t __get_FCSR(void);
|
|
extern void __set_FCSR(uint32_t value);
|
|
extern uint32_t __get_MSTATUS(void);
|
|
extern void __set_MSTATUS(uint32_t value);
|
|
extern uint32_t __get_MISA(void);
|
|
extern void __set_MISA(uint32_t value);
|
|
extern uint32_t __get_MTVEC(void);
|
|
extern void __set_MTVEC(uint32_t value);
|
|
extern uint32_t __get_MSCRATCH(void);
|
|
extern void __set_MSCRATCH(uint32_t value);
|
|
extern uint32_t __get_MEPC(void);
|
|
extern void __set_MEPC(uint32_t value);
|
|
extern uint32_t __get_MCAUSE(void);
|
|
extern void __set_MCAUSE(uint32_t value);
|
|
extern uint32_t __get_MTVAL(void);
|
|
extern void __set_MTVAL(uint32_t value);
|
|
extern uint32_t __get_MVENDORID(void);
|
|
extern uint32_t __get_MARCHID(void);
|
|
extern uint32_t __get_MIMPID(void);
|
|
extern uint32_t __get_MHARTID(void);
|
|
extern uint32_t __get_SP(void);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|