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Updated to EVT 1.5 

Signed-off-by: Yilin Sun <imi415@imi.moe>
This commit is contained in:
Yilin Sun 2024-02-04 23:02:42 +08:00
parent 49754ad11b
commit 5461772613
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
8 changed files with 1431 additions and 201 deletions
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6
Core/core_riscv.c
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@ -1,9 +1,9 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/06/06
* Description : RISC-V Core Peripheral Access Layer Source File
* Version : V1.0.1
* Date : 2023/11/11
* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32X035
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for

50
Core/core_riscv.h
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@ -1,9 +1,9 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.0
* Date : 2023/06/06
* Description : RISC-V Core Peripheral Access Layer Header File for CH32X035
* Version : V1.0.1
* Date : 2023/11/11
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32X035
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
@ -104,18 +104,18 @@ typedef struct{
/* memory mapped structure for SysTick */
typedef struct
{
__IO u32 CTLR;
__IO u32 SR;
__IO u64 CNT;
__IO u64 CMP;
__IO uint32_t CTLR;
__IO uint32_t SR;
__IO uint64_t CNT;
__IO uint64_t CMP;
}SysTick_Type;
#define PFIC ((PFIC_Type *) 0xE000E000 )
#define NVIC PFIC
#define NVIC_KEY1 ((uint32_t)0xFA050000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *) 0xE000F000)
@ -128,7 +128,7 @@ typedef struct
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
{
__asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
__asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
}
/*********************************************************************
@ -140,7 +140,7 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
__asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
}
/*********************************************************************
@ -262,9 +262,13 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn
* @brief Set Interrupt Priority
*
* @param IRQn - Interrupt Numbers
* priority: bit[7] - pre-emption priority
* bit[6:5] - subpriority
*
* interrupt nesting enable(CSR-0x804 bit1 = 1 bit[3:2] = 1)
* priority - bit[7] - Preemption Priority
* bit[6:4] - Sub priority
* bit[3:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0 bit[3:2] = 0)
* priority - bit[7:4] - Sub priority
* bit[3:0] - Reserve
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
@ -340,7 +344,8 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
{
if(num > 3) return ;
if (NewState != DISABLE)
@ -348,7 +353,8 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
}
else{
else
{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
}
@ -407,15 +413,15 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile
}
/*********************************************************************
* @fn __AMOMAX_W
* @fn __AMOMAX_W
*
* @brief Atomic signed MAX with 32bit value
* Atomically signed max compare 32bit value with value in memory using amomax.d.
* @brief Atomic signed MAX with 32bit value
* Atomically signed max compare 32bit value with value in memory using amomax.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the bigger value
* @return the bigger value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
{

312
Peripheral/inc/ch32x035.h
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@ -1,8 +1,8 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035.h
* Author : WCH
* Version : V1.0.0
* Date : 2023/04/06
* Version : V1.0.1
* Date : 2023/11/20
* Description : CH32X035 Device Peripheral Access Layer Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@ -23,7 +23,7 @@ extern "C" {
/* Standard Peripheral Library version number */
#define __STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */
#define __STDPERIPH_VERSION_SUB (0x03) /* [7:0] sub version */
#define __STDPERIPH_VERSION_SUB (0x05) /* [7:0] sub version */
#define __STDPERIPH_VERSION ((__STDPERIPH_VERSION_MAIN << 8)\
|(__STDPERIPH_VERSION_SUB << 0))
@ -1023,29 +1023,29 @@ typedef struct
#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */
/******************** Bit definition for ADC_CTLR3 register ********************/
#define ADC_CTLR3_CLK_DIV ((uint32_t)0x0000000F) /* CLK_DIVL[3:0] bits */
#define ADC_CTLR3_CLK_DIV_0 ((uint32_t)0x00000001) /* Bit 0 */
#define ADC_CTLR3_CLK_DIV_1 ((uint32_t)0x00000002) /* Bit 1 */
#define ADC_CTLR3_CLK_DIV_2 ((uint32_t)0x00000004) /* Bit 2 */
#define ADC_CTLR3_CLK_DIV_3 ((uint32_t)0x00000008) /* Bit 3 */
#define ADC_CTLR3_CLK_DIV ((uint32_t)0x0000000F) /* CLK_DIVL[3:0] bits */
#define ADC_CTLR3_CLK_DIV_0 ((uint32_t)0x00000001) /* Bit 0 */
#define ADC_CTLR3_CLK_DIV_1 ((uint32_t)0x00000002) /* Bit 1 */
#define ADC_CTLR3_CLK_DIV_2 ((uint32_t)0x00000004) /* Bit 2 */
#define ADC_CTLR3_CLK_DIV_3 ((uint32_t)0x00000008) /* Bit 3 */
#define ADC_CTLR3_AWD_SCAN ((uint32_t)0x00000200) /* Analog watchdog Scan enable */
#define ADC_CTLR3_AWD0_RST_EN ((uint32_t)0x00001000) /* Watchdog0 Reset Enable */
#define ADC_CTLR3_AWD1_RST_EN ((uint32_t)0x00002000) /* Watchdog1 Reset Enable */
#define ADC_CTLR3_AWD2_RST_EN ((uint32_t)0x00004000) /* Watchdog2 Reset Enable */
#define ADC_CTLR3_AWD3_RST_EN ((uint32_t)0x00008000) /* Watchdog3 Reset Enable */
#define ADC_CTLR3_AWD_SCAN ((uint32_t)0x00000200) /* Analog watchdog Scan enable */
#define ADC_CTLR3_AWD0_RST_EN ((uint32_t)0x00001000) /* Watchdog0 Reset Enable */
#define ADC_CTLR3_AWD1_RST_EN ((uint32_t)0x00002000) /* Watchdog1 Reset Enable */
#define ADC_CTLR3_AWD2_RST_EN ((uint32_t)0x00004000) /* Watchdog2 Reset Enable */
#define ADC_CTLR3_AWD3_RST_EN ((uint32_t)0x00008000) /* Watchdog3 Reset Enable */
/******************** Bit definition for ADC_WDTR1 register ********************/
#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog1 low threshold */
#define ADC_WDTR1_HTR1 ((uint32_t)0x00FFF000) /* Analog watchdog1 high threshold */
#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog1 low threshold */
#define ADC_WDTR1_HTR1 ((uint32_t)0x0FFF0000) /* Analog watchdog1 high threshold */
/******************** Bit definition for ADC_WDTR2 register ********************/
#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog2 low threshold */
#define ADC_WDTR2_HTR2 ((uint32_t)0x00FFF000) /* Analog watchdog2 high threshold */
#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog2 low threshold */
#define ADC_WDTR2_HTR2 ((uint32_t)0x0FFF0000) /* Analog watchdog2 high threshold */
/******************** Bit definition for ADC_WDTR3 register ********************/
#define ADC_WDTR3_LTR3 ((uint32_t)0x00000FFF) /* Analog watchdog3 low threshold */
#define ADC_WDTR3_HTR3 ((uint32_t)0x00FFF000) /* Analog watchdog3 high threshold */
#define ADC_WDTR3_LTR3 ((uint32_t)0x00000FFF) /* Analog watchdog3 low threshold */
#define ADC_WDTR3_HTR3 ((uint32_t)0x0FFF0000) /* Analog watchdog3 high threshold */
/******************************************************************************/
/* DMA Controller */
@ -1597,18 +1597,17 @@ typedef struct
/****************** Bit definition for FLASH_STATR register *******************/
#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */
#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */
#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */
#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */
#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */
#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */
#define FLASH_STATR_BOOT_AVA ((uint16_t)0x100) /* The state of Init Config */
#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x200) /* The source of Execute Program */
#define FLASH_STATR_BOOT_MODE ((uint16_t)0x400) /* The switch of user section or boot section*/
#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x800) /* Lock boot area*/
#define FLASH_STATR_BOOT_AVA ((uint16_t)0x1000) /* The state of Init Config */
#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x2000) /* The source of Execute Program */
#define FLASH_STATR_BOOT_MODE ((uint16_t)0x4000) /* The switch of user section or boot section*/
#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x8000) /* Lock boot area*/
/******************* Bit definition for FLASH_CTLR register *******************/
#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */
#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */
#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */
#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */
@ -1640,8 +1639,8 @@ typedef struct
#define FLASH_OBR_CFGRSTT ((uint16_t)0x0060) /* Config Reset delay time */
#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* fix 11 */
#define FLASH_OBR_DATA0 ((uint32_t)0x3FC00) /* Data byte0 */
#define FLASH_OBR_DATA1 ((uint32_t)0x3FC0000) /* Data byte1 */
#define FLASH_OBR_DATA0 ((uint32_t)0x0003FC00) /* Data byte0 */
#define FLASH_OBR_DATA1 ((uint32_t)0x03FC0000) /* Data byte1 */
/****************** Bit definition for FLASH_WPR register ******************/
#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */
@ -1975,90 +1974,90 @@ typedef struct
/******************* Bit definition for GPIO_CFGXR register *******************/
#define GPIO_CFGXR_MODE ((uint32_t)0x33333333) /* Port x mode bits */
#define GPIO_CFGXR_MODE16 ((uint32_t)0x00000003) /* MODE16[1:0] bits (Port x mode bits, pin 0) */
#define GPIO_CFGXR_MODE16_0 ((uint32_t)0x00000001) /* Bit 0 */
#define GPIO_CFGXR_MODE16_1 ((uint32_t)0x00000002) /* Bit 1 */
#define GPIO_CFGXR_MODE16 ((uint32_t)0x00000003) /* MODE16[1:0] bits (Port x mode bits, pin 0) */
#define GPIO_CFGXR_MODE16_0 ((uint32_t)0x00000001) /* Bit 0 */
#define GPIO_CFGXR_MODE16_1 ((uint32_t)0x00000002) /* Bit 1 */
#define GPIO_CFGXR_MODE17 ((uint32_t)0x00000030) /* MODE17[1:0] bits (Port x mode bits, pin 1) */
#define GPIO_CFGXR_MODE17_0 ((uint32_t)0x00000010) /* Bit 0 */
#define GPIO_CFGXR_MODE17_1 ((uint32_t)0x00000020) /* Bit 1 */
#define GPIO_CFGXR_MODE17 ((uint32_t)0x00000030) /* MODE17[1:0] bits (Port x mode bits, pin 1) */
#define GPIO_CFGXR_MODE17_0 ((uint32_t)0x00000010) /* Bit 0 */
#define GPIO_CFGXR_MODE17_1 ((uint32_t)0x00000020) /* Bit 1 */
#define GPIO_CFGXR_MODE18 ((uint32_t)0x00000300) /* MODE18[1:0] bits (Port x mode bits, pin 2) */
#define GPIO_CFGXR_MODE18_0 ((uint32_t)0x00000100) /* Bit 0 */
#define GPIO_CFGXR_MODE18_1 ((uint32_t)0x00000200) /* Bit 1 */
#define GPIO_CFGXR_MODE18 ((uint32_t)0x00000300) /* MODE18[1:0] bits (Port x mode bits, pin 2) */
#define GPIO_CFGXR_MODE18_0 ((uint32_t)0x00000100) /* Bit 0 */
#define GPIO_CFGXR_MODE18_1 ((uint32_t)0x00000200) /* Bit 1 */
#define GPIO_CFGXR_MODE19 ((uint32_t)0x00003000) /* MODE19[1:0] bits (Port x mode bits, pin 3) */
#define GPIO_CFGXR_MODE19_0 ((uint32_t)0x00001000) /* Bit 0 */
#define GPIO_CFGXR_MODE19_1 ((uint32_t)0x00002000) /* Bit 1 */
#define GPIO_CFGXR_MODE19 ((uint32_t)0x00003000) /* MODE19[1:0] bits (Port x mode bits, pin 3) */
#define GPIO_CFGXR_MODE19_0 ((uint32_t)0x00001000) /* Bit 0 */
#define GPIO_CFGXR_MODE19_1 ((uint32_t)0x00002000) /* Bit 1 */
#define GPIO_CFGXR_MODE20 ((uint32_t)0x00030000) /* MODE20[1:0] bits (Port x mode bits, pin 4) */
#define GPIO_CFGXR_MODE20_0 ((uint32_t)0x00010000) /* Bit 0 */
#define GPIO_CFGXR_MODE20_1 ((uint32_t)0x00020000) /* Bit 1 */
#define GPIO_CFGXR_MODE20 ((uint32_t)0x00030000) /* MODE20[1:0] bits (Port x mode bits, pin 4) */
#define GPIO_CFGXR_MODE20_0 ((uint32_t)0x00010000) /* Bit 0 */
#define GPIO_CFGXR_MODE20_1 ((uint32_t)0x00020000) /* Bit 1 */
#define GPIO_CFGXR_MODE21 ((uint32_t)0x00300000) /* MODE21[1:0] bits (Port x mode bits, pin 5) */
#define GPIO_CFGXR_MODE21_0 ((uint32_t)0x00100000) /* Bit 0 */
#define GPIO_CFGXR_MODE21_1 ((uint32_t)0x00200000) /* Bit 1 */
#define GPIO_CFGXR_MODE21 ((uint32_t)0x00300000) /* MODE21[1:0] bits (Port x mode bits, pin 5) */
#define GPIO_CFGXR_MODE21_0 ((uint32_t)0x00100000) /* Bit 0 */
#define GPIO_CFGXR_MODE21_1 ((uint32_t)0x00200000) /* Bit 1 */
#define GPIO_CFGXR_MODE22 ((uint32_t)0x03000000) /* MODE22[1:0] bits (Port x mode bits, pin 6) */
#define GPIO_CFGXR_MODE22_0 ((uint32_t)0x01000000) /* Bit 0 */
#define GPIO_CFGXR_MODE22_1 ((uint32_t)0x02000000) /* Bit 1 */
#define GPIO_CFGXR_MODE22 ((uint32_t)0x03000000) /* MODE22[1:0] bits (Port x mode bits, pin 6) */
#define GPIO_CFGXR_MODE22_0 ((uint32_t)0x01000000) /* Bit 0 */
#define GPIO_CFGXR_MODE22_1 ((uint32_t)0x02000000) /* Bit 1 */
#define GPIO_CFGXR_MODE23 ((uint32_t)0x30000000) /* MODE23[1:0] bits (Port x mode bits, pin 7) */
#define GPIO_CFGXR_MODE23_0 ((uint32_t)0x10000000) /* Bit 0 */
#define GPIO_CFGXR_MODE23_1 ((uint32_t)0x20000000) /* Bit 1 */
#define GPIO_CFGXR_MODE23 ((uint32_t)0x30000000) /* MODE23[1:0] bits (Port x mode bits, pin 7) */
#define GPIO_CFGXR_MODE23_0 ((uint32_t)0x10000000) /* Bit 0 */
#define GPIO_CFGXR_MODE23_1 ((uint32_t)0x20000000) /* Bit 1 */
#define GPIO_CFGXR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
#define GPIO_CFGXR_CNF16 ((uint32_t)0x0000000C) /* CNF16[1:0] bits (Port x configuration bits, pin 0) */
#define GPIO_CFGXR_CNF16_0 ((uint32_t)0x00000004) /* Bit 0 */
#define GPIO_CFGXR_CNF16_1 ((uint32_t)0x00000008) /* Bit 1 */
#define GPIO_CFGXR_CNF16 ((uint32_t)0x0000000C) /* CNF16[1:0] bits (Port x configuration bits, pin 0) */
#define GPIO_CFGXR_CNF16_0 ((uint32_t)0x00000004) /* Bit 0 */
#define GPIO_CFGXR_CNF16_1 ((uint32_t)0x00000008) /* Bit 1 */
#define GPIO_CFGXR_CNF17 ((uint32_t)0x000000C0) /* CNF17[1:0] bits (Port x configuration bits, pin 1) */
#define GPIO_CFGXR_CNF17_0 ((uint32_t)0x00000040) /* Bit 0 */
#define GPIO_CFGXR_CNF17_1 ((uint32_t)0x00000080) /* Bit 1 */
#define GPIO_CFGXR_CNF17 ((uint32_t)0x000000C0) /* CNF17[1:0] bits (Port x configuration bits, pin 1) */
#define GPIO_CFGXR_CNF17_0 ((uint32_t)0x00000040) /* Bit 0 */
#define GPIO_CFGXR_CNF17_1 ((uint32_t)0x00000080) /* Bit 1 */
#define GPIO_CFGXR_CNF18 ((uint32_t)0x00000C00) /* CNF18[1:0] bits (Port x configuration bits, pin 2) */
#define GPIO_CFGXR_CNF18_0 ((uint32_t)0x00000400) /* Bit 0 */
#define GPIO_CFGXR_CNF18_1 ((uint32_t)0x00000800) /* Bit 1 */
#define GPIO_CFGXR_CNF18 ((uint32_t)0x00000C00) /* CNF18[1:0] bits (Port x configuration bits, pin 2) */
#define GPIO_CFGXR_CNF18_0 ((uint32_t)0x00000400) /* Bit 0 */
#define GPIO_CFGXR_CNF18_1 ((uint32_t)0x00000800) /* Bit 1 */
#define GPIO_CFGXR_CNF19 ((uint32_t)0x0000C000) /* CNF19[1:0] bits (Port x configuration bits, pin 3) */
#define GPIO_CFGXR_CNF19_0 ((uint32_t)0x00004000) /* Bit 0 */
#define GPIO_CFGXR_CNF19_1 ((uint32_t)0x00008000) /* Bit 1 */
#define GPIO_CFGXR_CNF19 ((uint32_t)0x0000C000) /* CNF19[1:0] bits (Port x configuration bits, pin 3) */
#define GPIO_CFGXR_CNF19_0 ((uint32_t)0x00004000) /* Bit 0 */
#define GPIO_CFGXR_CNF19_1 ((uint32_t)0x00008000) /* Bit 1 */
#define GPIO_CFGXR_CNF20 ((uint32_t)0x000C0000) /* CNF20[1:0] bits (Port x configuration bits, pin 4) */
#define GPIO_CFGXR_CNF20_0 ((uint32_t)0x00040000) /* Bit 0 */
#define GPIO_CFGXR_CNF20_1 ((uint32_t)0x00080000) /* Bit 1 */
#define GPIO_CFGXR_CNF20 ((uint32_t)0x000C0000) /* CNF20[1:0] bits (Port x configuration bits, pin 4) */
#define GPIO_CFGXR_CNF20_0 ((uint32_t)0x00040000) /* Bit 0 */
#define GPIO_CFGXR_CNF20_1 ((uint32_t)0x00080000) /* Bit 1 */
#define GPIO_CFGXR_CNF21 ((uint32_t)0x00C00000) /* CNF21[1:0] bits (Port x configuration bits, pin 5) */
#define GPIO_CFGXR_CNF21_0 ((uint32_t)0x00400000) /* Bit 0 */
#define GPIO_CFGXR_CNF21_1 ((uint32_t)0x00800000) /* Bit 1 */
#define GPIO_CFGXR_CNF21 ((uint32_t)0x00C00000) /* CNF21[1:0] bits (Port x configuration bits, pin 5) */
#define GPIO_CFGXR_CNF21_0 ((uint32_t)0x00400000) /* Bit 0 */
#define GPIO_CFGXR_CNF21_1 ((uint32_t)0x00800000) /* Bit 1 */
#define GPIO_CFGXR_CNF22 ((uint32_t)0x0C000000) /* CNF22[1:0] bits (Port x configuration bits, pin 6) */
#define GPIO_CFGXR_CNF22_0 ((uint32_t)0x04000000) /* Bit 0 */
#define GPIO_CFGXR_CNF22_1 ((uint32_t)0x08000000) /* Bit 1 */
#define GPIO_CFGXR_CNF22 ((uint32_t)0x0C000000) /* CNF22[1:0] bits (Port x configuration bits, pin 6) */
#define GPIO_CFGXR_CNF22_0 ((uint32_t)0x04000000) /* Bit 0 */
#define GPIO_CFGXR_CNF22_1 ((uint32_t)0x08000000) /* Bit 1 */
#define GPIO_CFGXR_CNF23 ((uint32_t)0xC0000000) /* CNF23[1:0] bits (Port x configuration bits, pin 7) */
#define GPIO_CFGXR_CNF23_0 ((uint32_t)0x40000000) /* Bit 0 */
#define GPIO_CFGXR_CNF23_1 ((uint32_t)0x80000000) /* Bit 1 */
#define GPIO_CFGXR_CNF23 ((uint32_t)0xC0000000) /* CNF23[1:0] bits (Port x configuration bits, pin 7) */
#define GPIO_CFGXR_CNF23_0 ((uint32_t)0x40000000) /* Bit 0 */
#define GPIO_CFGXR_CNF23_1 ((uint32_t)0x80000000) /* Bit 1 */
/****************** Bit definition for GPIO_BSXR register *******************/
#define GPIO_BSXR_BS16 ((uint32_t)0x00000001) /* Port x Set bit 0 */
#define GPIO_BSXR_BS17 ((uint32_t)0x00000002) /* Port x Set bit 1 */
#define GPIO_BSXR_BS18 ((uint32_t)0x00000004) /* Port x Set bit 2 */
#define GPIO_BSXR_BS19 ((uint32_t)0x00000008) /* Port x Set bit 3 */
#define GPIO_BSXR_BS20 ((uint32_t)0x00000010) /* Port x Set bit 4 */
#define GPIO_BSXR_BS21 ((uint32_t)0x00000020) /* Port x Set bit 5 */
#define GPIO_BSXR_BS22 ((uint32_t)0x00000040) /* Port x Set bit 6 */
#define GPIO_BSXR_BS23 ((uint32_t)0x00000080) /* Port x Set bit 7 */
#define GPIO_BSXR_BS16 ((uint32_t)0x00000001) /* Port x Set bit 0 */
#define GPIO_BSXR_BS17 ((uint32_t)0x00000002) /* Port x Set bit 1 */
#define GPIO_BSXR_BS18 ((uint32_t)0x00000004) /* Port x Set bit 2 */
#define GPIO_BSXR_BS19 ((uint32_t)0x00000008) /* Port x Set bit 3 */
#define GPIO_BSXR_BS20 ((uint32_t)0x00000010) /* Port x Set bit 4 */
#define GPIO_BSXR_BS21 ((uint32_t)0x00000020) /* Port x Set bit 5 */
#define GPIO_BSXR_BS22 ((uint32_t)0x00000040) /* Port x Set bit 6 */
#define GPIO_BSXR_BS23 ((uint32_t)0x00000080) /* Port x Set bit 7 */
#define GPIO_BSXR_BR16 ((uint32_t)0x00010000) /* Port x Reset bit 0 */
#define GPIO_BSXR_BR17 ((uint32_t)0x00020000) /* Port x Reset bit 1 */
#define GPIO_BSXR_BR18 ((uint32_t)0x00040000) /* Port x Reset bit 2 */
#define GPIO_BSXR_BR19 ((uint32_t)0x00080000) /* Port x Reset bit 3 */
#define GPIO_BSXR_BR20 ((uint32_t)0x00100000) /* Port x Reset bit 4 */
#define GPIO_BSXR_BR21 ((uint32_t)0x00200000) /* Port x Reset bit 5 */
#define GPIO_BSXR_BR22 ((uint32_t)0x00400000) /* Port x Reset bit 6 */
#define GPIO_BSXR_BR23 ((uint32_t)0x00800000) /* Port x Reset bit 7 */
#define GPIO_BSXR_BR16 ((uint32_t)0x00010000) /* Port x Reset bit 0 */
#define GPIO_BSXR_BR17 ((uint32_t)0x00020000) /* Port x Reset bit 1 */
#define GPIO_BSXR_BR18 ((uint32_t)0x00040000) /* Port x Reset bit 2 */
#define GPIO_BSXR_BR19 ((uint32_t)0x00080000) /* Port x Reset bit 3 */
#define GPIO_BSXR_BR20 ((uint32_t)0x00100000) /* Port x Reset bit 4 */
#define GPIO_BSXR_BR21 ((uint32_t)0x00200000) /* Port x Reset bit 5 */
#define GPIO_BSXR_BR22 ((uint32_t)0x00400000) /* Port x Reset bit 6 */
#define GPIO_BSXR_BR23 ((uint32_t)0x00800000) /* Port x Reset bit 7 */
/****************** Bit definition for AFIO_PCFR1register *******************/
#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000003) /* SPI1_REMAP[1:0] bits (SPI1 remapping) */
@ -2083,31 +2082,31 @@ typedef struct
#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */
#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */
#define AFIO_PCFR1_USART4_REMAP ((uint32_t)0x00000700) /* USART4_REMAP[14:12] bits (USART4 remapping) */
#define AFIO_PCFR1_USART4_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */
#define AFIO_PCFR1_USART4_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */
#define AFIO_PCFR1_USART4_REMAP_2 ((uint32_t)0x00000400) /* Bit 2 */
#define AFIO_PCFR1_USART4_REMAP ((uint32_t)0x00007000) /* USART4_REMAP[14:12] bits (USART4 remapping) */
#define AFIO_PCFR1_USART4_REMAP_0 ((uint32_t)0x00001000) /* Bit 0 */
#define AFIO_PCFR1_USART4_REMAP_1 ((uint32_t)0x00002000) /* Bit 1 */
#define AFIO_PCFR1_USART4_REMAP_2 ((uint32_t)0x00004000) /* Bit 2 */
#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00003800) /* TIM1_REMAP[17:15] bits (TIM1 remapping) */
#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000800) /* Bit 0 */
#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00001000) /* Bit 1 */
#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00002000) /* Bit 2 */
#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00038000) /* TIM1_REMAP[17:15] bits (TIM1 remapping) */
#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00008000) /* Bit 0 */
#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00010000) /* Bit 1 */
#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00020000) /* Bit 2 */
#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x0001C000) /* TIM2_REMAP[20:18] bits (TIM2 remapping) */
#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00004000) /* Bit 0 */
#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00008000) /* Bit 1 */
#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00010000) /* Bit 2 */
#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x001C0000) /* TIM2_REMAP[20:18] bits (TIM2 remapping) */
#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00040000) /* Bit 0 */
#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00080000) /* Bit 1 */
#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00100000) /* Bit 2 */
#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00060000) /* TIM3_REMAP[22:21] bits (TIM3 remapping) */
#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00020000) /* Bit 0 */
#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00040000) /* Bit 1 */
#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00600000) /* TIM3_REMAP[22:21] bits (TIM3 remapping) */
#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00200000) /* Bit 0 */
#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00400000) /* Bit 1 */
#define AFIO_PCFR1_PIOC_REMAP ((uint32_t)0x00080000) /* PIOC[23] bits (PIOC remapping) */
#define AFIO_PCFR1_PIOC_REMAP ((uint32_t)0x00800000) /* PIOC[23] bits (PIOC remapping) */
#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x00700000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x00100000) /* Bit 0 */
#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x00200000) /* Bit 1 */
#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x00400000) /* Bit 2 */
#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */
#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */
#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */
/***************** Bit definition for AFIO_EXTICR1 register *****************/
#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */
@ -2201,60 +2200,59 @@ typedef struct
#define AFIO_EXTICR2_EXTI22 ((uint32_t)0x00003000) /* EXTI 22 configuration */
#define AFIO_EXTICR2_EXTI23 ((uint32_t)0x0000C000) /* EXTI 23 configuration */
#define AFIO_EXTICR2_EXTI16_PA ((uint32_t)0x00000000) /* PA[16] pin */
#define AFIO_EXTICR2_EXTI16_PB ((uint32_t)0x00000001) /* PB[16] pin */
#define AFIO_EXTICR2_EXTI16_PC ((uint32_t)0x00000002) /* PC[16] pin */
#define AFIO_EXTICR2_EXTI16_PA ((uint32_t)0x00000000) /* PA[16] pin */
#define AFIO_EXTICR2_EXTI16_PB ((uint32_t)0x00000001) /* PB[16] pin */
#define AFIO_EXTICR2_EXTI16_PC ((uint32_t)0x00000002) /* PC[16] pin */
#define AFIO_EXTICR2_EXTI17_PA ((uint32_t)0x00000000) /* PA[17] pin */
#define AFIO_EXTICR2_EXTI17_PB ((uint32_t)0x00000004) /* PB[17] pin */
#define AFIO_EXTICR2_EXTI17_PC ((uint32_t)0x00000008) /* PC[17] pin */
#define AFIO_EXTICR2_EXTI17_PA ((uint32_t)0x00000000) /* PA[17] pin */
#define AFIO_EXTICR2_EXTI17_PB ((uint32_t)0x00000004) /* PB[17] pin */
#define AFIO_EXTICR2_EXTI17_PC ((uint32_t)0x00000008) /* PC[17] pin */
#define AFIO_EXTICR2_EXTI18_PA ((uint32_t)0x00000000) /* PA[18] pin */
#define AFIO_EXTICR2_EXTI18_PB ((uint32_t)0x00000010) /* PB[18] pin */
#define AFIO_EXTICR2_EXTI18_PC ((uint32_t)0x00000020) /* PC[18] pin */
#define AFIO_EXTICR2_EXTI18_PA ((uint32_t)0x00000000) /* PA[18] pin */
#define AFIO_EXTICR2_EXTI18_PB ((uint32_t)0x00000010) /* PB[18] pin */
#define AFIO_EXTICR2_EXTI18_PC ((uint32_t)0x00000020) /* PC[18] pin */
#define AFIO_EXTICR2_EXTI19_PA ((uint32_t)0x00000000) /* PA[19] pin */
#define AFIO_EXTICR2_EXTI19_PB ((uint32_t)0x00000040) /* PB[19] pin */
#define AFIO_EXTICR2_EXTI19_PC ((uint32_t)0x00000080) /* PC[19] pin */
#define AFIO_EXTICR2_EXTI19_PA ((uint32_t)0x00000000) /* PA[19] pin */
#define AFIO_EXTICR2_EXTI19_PB ((uint32_t)0x00000040) /* PB[19] pin */
#define AFIO_EXTICR2_EXTI19_PC ((uint32_t)0x00000080) /* PC[19] pin */
#define AFIO_EXTICR2_EXTI20_PA ((uint32_t)0x00000000) /* PA[20] pin */
#define AFIO_EXTICR2_EXTI20_PB ((uint32_t)0x00000100) /* PB[20] pin */
#define AFIO_EXTICR2_EXTI20_PC ((uint32_t)0x00000200) /* PC[20] pin */
#define AFIO_EXTICR2_EXTI20_PA ((uint32_t)0x00000000) /* PA[20] pin */
#define AFIO_EXTICR2_EXTI20_PB ((uint32_t)0x00000100) /* PB[20] pin */
#define AFIO_EXTICR2_EXTI20_PC ((uint32_t)0x00000200) /* PC[20] pin */
#define AFIO_EXTICR2_EXTI21_PA ((uint32_t)0x00000000) /* PA[21] pin */
#define AFIO_EXTICR2_EXTI21_PB ((uint32_t)0x00000400) /* PB[21] pin */
#define AFIO_EXTICR2_EXTI21_PC ((uint32_t)0x00000800) /* PC[21] pin */
#define AFIO_EXTICR2_EXTI21_PA ((uint32_t)0x00000000) /* PA[21] pin */
#define AFIO_EXTICR2_EXTI21_PB ((uint32_t)0x00000400) /* PB[21] pin */
#define AFIO_EXTICR2_EXTI21_PC ((uint32_t)0x00000800) /* PC[21] pin */
#define AFIO_EXTICR2_EXTI22_PA ((uint32_t)0x00000000) /* PA[22] pin */
#define AFIO_EXTICR2_EXTI22_PB ((uint32_t)0x00001000) /* PB[22] pin */
#define AFIO_EXTICR2_EXTI22_PC ((uint32_t)0x00002000) /* PC[22] pin */
#define AFIO_EXTICR2_EXTI22_PA ((uint32_t)0x00000000) /* PA[22] pin */
#define AFIO_EXTICR2_EXTI22_PB ((uint32_t)0x00001000) /* PB[22] pin */
#define AFIO_EXTICR2_EXTI22_PC ((uint32_t)0x00002000) /* PC[22] pin */
#define AFIO_EXTICR2_EXTI23_PA ((uint32_t)0x00000000) /* PA[23] pin */
#define AFIO_EXTICR2_EXTI23_PB ((uint32_t)0x00004000) /* PB[23] pin */
#define AFIO_EXTICR2_EXTI23_PC ((uint32_t)0x00008000) /* PC[23] pin */
#define AFIO_EXTICR2_EXTI23_PA ((uint32_t)0x00000000) /* PA[23] pin */
#define AFIO_EXTICR2_EXTI23_PB ((uint32_t)0x00004000) /* PB[23] pin */
#define AFIO_EXTICR2_EXTI23_PC ((uint32_t)0x00008000) /* PC[23] pin */
/******************* Bit definition for AFIO_CTLR register ********************/
#define AFIO_CTLR_UDM_PUE ((uint32_t)0x00000003) /* PC16/UDM Pin pull-up Mode*/
#define AFIO_CTLR_UDM_PUE_0 ((uint32_t)0x00000001) /* bit[0] */
#define AFIO_CTLR_UDM_PUE_1 ((uint32_t)0x00000002) /* bit[1] */
#define AFIO_CTLR_UDM_PUE ((uint32_t)0x00000003) /* PC16/UDM Pin pull-up Mode*/
#define AFIO_CTLR_UDM_PUE_0 ((uint32_t)0x00000001) /* bit[0] */
#define AFIO_CTLR_UDM_PUE_1 ((uint32_t)0x00000002) /* bit[1] */
#define AFIO_CTLR_UDP_PUE ((uint32_t)0x00000000) /* PC17/UDP Pin pull-up Mode*/
#define AFIO_CTLR_UDP_PUE_0 ((uint32_t)0x00000004) /* bit[2] */
#define AFIO_CTLR_UDP_PUE_1 ((uint32_t)0x00000008) /* bit[3] */
#define AFIO_CTLR_USB_PHY_V33 ((uint32_t)0x00000040) /* USB transceiver PHY output and pull-up limiter configuration */
#define AFIO_CTLR_USB_IOEN ((uint32_t)0x00000080) /* USB Remap pin enable */
#define AFIO_CTLR_USBPD_PHY_V33 ((uint32_t)0x00000100) /* USBPD transceiver PHY output and pull-up limiter configuration */
#define AFIO_CTLR_USBPD_IN_HVT ((uint32_t)0x00000200) /* PD pin PC14/PC15 high threshold input mode */
#define AFIO_CTLR_UDP_BC_VSRC ((uint32_t)0x00010000) /* PC17/UDP pin BC protocol source voltage enable */
#define AFIO_CTLR_UDM_BC_VSRC ((uint32_t)0x00020000) /* PC16/UDM pin BC protocol source voltage enable */
#define AFIO_CTLR_UDP_BC_CMPO ((uint32_t)0x00040000) /* PC17/UDP pin BC protocol comparator status */
#define AFIO_CTLR_UDM_BC_CMPO ((uint32_t)0x00080000) /* PC16/UDM pin BC protocol comparator status */
#define AFIO_CTLR_PA3_FILT_EN ((uint32_t)0x01000000) /* Controls the input filtering of the PA3 pin */
#define AFIO_CTLR_PA4_FILT_EN ((uint32_t)0x02000000) /* Controls the input filtering of the PA4 pin */
#define AFIO_CTLR_PB5_FILT_EN ((uint32_t)0x04000000) /* Controls the input filtering of the PB5 pin */
#define AFIO_CTLR_PB6_FILT_EN ((uint32_t)0x08000000) /* Controls the input filtering of the PB6 pin */
#define AFIO_CTLR_UDP_PUE ((uint32_t)0x0000000C) /* PC17/UDP Pin pull-up Mode*/
#define AFIO_CTLR_UDP_PUE_0 ((uint32_t)0x00000004) /* bit[2] */
#define AFIO_CTLR_UDP_PUE_1 ((uint32_t)0x00000008) /* bit[3] */
#define AFIO_CTLR_USB_PHY_V33 ((uint32_t)0x00000040) /* USB transceiver PHY output and pull-up limiter configuration */
#define AFIO_CTLR_USB_IOEN ((uint32_t)0x00000080) /* USB Remap pin enable */
#define AFIO_CTLR_USBPD_PHY_V33 ((uint32_t)0x00000100) /* USBPD transceiver PHY output and pull-up limiter configuration */
#define AFIO_CTLR_USBPD_IN_HVT ((uint32_t)0x00000200) /* PD pin PC14/PC15 high threshold input mode */
#define AFIO_CTLR_UDP_BC_VSRC ((uint32_t)0x00010000) /* PC17/UDP pin BC protocol source voltage enable */
#define AFIO_CTLR_UDM_BC_VSRC ((uint32_t)0x00020000) /* PC16/UDM pin BC protocol source voltage enable */
#define AFIO_CTLR_UDP_BC_CMPO ((uint32_t)0x00040000) /* PC17/UDP pin BC protocol comparator status */
#define AFIO_CTLR_UDM_BC_CMPO ((uint32_t)0x00080000) /* PC16/UDM pin BC protocol comparator status */
#define AFIO_CTLR_PA3_FILT_EN ((uint32_t)0x01000000) /* Controls the input filtering of the PA3 pin */
#define AFIO_CTLR_PA4_FILT_EN ((uint32_t)0x02000000) /* Controls the input filtering of the PA4 pin */
#define AFIO_CTLR_PB5_FILT_EN ((uint32_t)0x04000000) /* Controls the input filtering of the PB5 pin */
#define AFIO_CTLR_PB6_FILT_EN ((uint32_t)0x08000000) /* Controls the input filtering of the PB6 pin */
/******************************************************************************/
/* Independent WATCHDOG */
@ -2291,7 +2289,7 @@ typedef struct
#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */
#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */
#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */
#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */
#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */
/******************* Bit definition for I2C_CTLR2 register ********************/
@ -2779,15 +2777,19 @@ typedef struct
/******************* Bit definition for TIM_CH1CVR register *******************/
#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */
#define TIM_LEVEL1 ((uint32_t)0x00010000)
/******************* Bit definition for TIM_CH2CVR register *******************/
#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */
#define TIM_LEVEL2 ((uint32_t)0x00010000)
/******************* Bit definition for TIM_CH3CVR register *******************/
#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */
#define TIM_LEVEL3 ((uint32_t)0x00010000)
/******************* Bit definition for TIM_CH4CVR register *******************/
#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */
#define TIM_LEVEL4 ((uint32_t)0x00010000)
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */

7
Peripheral/inc/ch32x035_flash.h
View File

@ -27,7 +27,10 @@ typedef enum
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT,
FLASH_RDP
FLASH_RDP,
FLASH_OP_RANGE_ERROR = 0xFD,
FLASH_ALIGN_ERROR = 0xFE,
FLASH_ADR_RANGE_ERROR = 0xFF,
} FLASH_Status;
/* Flash_Latency */
@ -135,6 +138,8 @@ void FLASH_BufLoad(uint32_t Address, uint32_t Data0);
void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address);
void SystemReset_StartMode(uint32_t Mode);
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
#ifdef __cplusplus

522
Peripheral/inc/ch32x035_usb.h Normal file
View File

@ -0,0 +1,522 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_usb.h
* Author : WCH
* Version : V1.0.0
* Date : 2023/04/06
* Description : This file contains all the functions prototypes for the USB
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32X035_USB_H
#define __CH32X035_USB_H
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************/
/* Header File */
#include "stdint.h"
/*******************************************************************************/
/* USB Communication Related Macro Definition */
/* USB PID */
#ifndef USB_PID_SETUP
#define USB_PID_NULL 0x00
#define USB_PID_SOF 0x05
#define USB_PID_SETUP 0x0D
#define USB_PID_IN 0x09
#define USB_PID_OUT 0x01
#define USB_PID_NYET 0x06
#define USB_PID_ACK 0x02
#define USB_PID_NAK 0x0A
#define USB_PID_STALL 0x0E
#define USB_PID_DATA0 0x03
#define USB_PID_DATA1 0x0B
#define USB_PID_PRE 0x0C
#endif
/* USB standard device request code */
#ifndef USB_GET_DESCRIPTOR
#define USB_GET_STATUS 0x00
#define USB_CLEAR_FEATURE 0x01
#define USB_SET_FEATURE 0x03
#define USB_SET_ADDRESS 0x05
#define USB_GET_DESCRIPTOR 0x06
#define USB_SET_DESCRIPTOR 0x07
#define USB_GET_CONFIGURATION 0x08
#define USB_SET_CONFIGURATION 0x09
#define USB_GET_INTERFACE 0x0A
#define USB_SET_INTERFACE 0x0B
#define USB_SYNCH_FRAME 0x0C
#endif
#define DEF_STRING_DESC_LANG 0x00
#define DEF_STRING_DESC_MANU 0x01
#define DEF_STRING_DESC_PROD 0x02
#define DEF_STRING_DESC_SERN 0x03
/* USB hub class request code */
#ifndef HUB_GET_DESCRIPTOR
#define HUB_GET_STATUS 0x00
#define HUB_CLEAR_FEATURE 0x01
#define HUB_GET_STATE 0x02
#define HUB_SET_FEATURE 0x03
#define HUB_GET_DESCRIPTOR 0x06
#define HUB_SET_DESCRIPTOR 0x07
#endif
/* USB HID class request code */
#ifndef HID_GET_REPORT
#define HID_GET_REPORT 0x01
#define HID_GET_IDLE 0x02
#define HID_GET_PROTOCOL 0x03
#define HID_SET_REPORT 0x09
#define HID_SET_IDLE 0x0A
#define HID_SET_PROTOCOL 0x0B
#endif
/* Bit Define for USB Request Type */
#ifndef USB_REQ_TYP_MASK
#define USB_REQ_TYP_IN 0x80
#define USB_REQ_TYP_OUT 0x00
#define USB_REQ_TYP_READ 0x80
#define USB_REQ_TYP_WRITE 0x00
#define USB_REQ_TYP_MASK 0x60
#define USB_REQ_TYP_STANDARD 0x00
#define USB_REQ_TYP_CLASS 0x20
#define USB_REQ_TYP_VENDOR 0x40
#define USB_REQ_TYP_RESERVED 0x60
#define USB_REQ_RECIP_MASK 0x1F
#define USB_REQ_RECIP_DEVICE 0x00
#define USB_REQ_RECIP_INTERF 0x01
#define USB_REQ_RECIP_ENDP 0x02
#define USB_REQ_RECIP_OTHER 0x03
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
#define USB_REQ_FEAT_ENDP_HALT 0x00
#endif
/* USB Descriptor Type */
#ifndef USB_DESCR_TYP_DEVICE
#define USB_DESCR_TYP_DEVICE 0x01
#define USB_DESCR_TYP_CONFIG 0x02
#define USB_DESCR_TYP_STRING 0x03
#define USB_DESCR_TYP_INTERF 0x04
#define USB_DESCR_TYP_ENDP 0x05
#define USB_DESCR_TYP_QUALIF 0x06
#define USB_DESCR_TYP_SPEED 0x07
#define USB_DESCR_TYP_OTG 0x09
#define USB_DESCR_TYP_BOS 0X0F
#define USB_DESCR_TYP_HID 0x21
#define USB_DESCR_TYP_REPORT 0x22
#define USB_DESCR_TYP_PHYSIC 0x23
#define USB_DESCR_TYP_CS_INTF 0x24
#define USB_DESCR_TYP_CS_ENDP 0x25
#define USB_DESCR_TYP_HUB 0x29
#endif
/* USB Device Class */
#ifndef USB_DEV_CLASS_HUB
#define USB_DEV_CLASS_RESERVED 0x00
#define USB_DEV_CLASS_AUDIO 0x01
#define USB_DEV_CLASS_COMMUNIC 0x02
#define USB_DEV_CLASS_HID 0x03
#define USB_DEV_CLASS_MONITOR 0x04
#define USB_DEV_CLASS_PHYSIC_IF 0x05
#define USB_DEV_CLASS_POWER 0x06
#define USB_DEV_CLASS_PRINTER 0x07
#define USB_DEV_CLASS_STORAGE 0x08
#define USB_DEV_CLASS_HUB 0x09
#define USB_DEV_CLASS_VEN_SPEC 0xFF
#endif
/* USB Hub Class Request */
#ifndef HUB_GET_HUB_DESCRIPTOR
#define HUB_CLEAR_HUB_FEATURE 0x20
#define HUB_CLEAR_PORT_FEATURE 0x23
#define HUB_GET_BUS_STATE 0xA3
#define HUB_GET_HUB_DESCRIPTOR 0xA0
#define HUB_GET_HUB_STATUS 0xA0
#define HUB_GET_PORT_STATUS 0xA3
#define HUB_SET_HUB_DESCRIPTOR 0x20
#define HUB_SET_HUB_FEATURE 0x20
#define HUB_SET_PORT_FEATURE 0x23
#endif
/* Hub Class Feature Selectors */
#ifndef HUB_PORT_RESET
#define HUB_C_HUB_LOCAL_POWER 0
#define HUB_C_HUB_OVER_CURRENT 1
#define HUB_PORT_CONNECTION 0
#define HUB_PORT_ENABLE 1
#define HUB_PORT_SUSPEND 2
#define HUB_PORT_OVER_CURRENT 3
#define HUB_PORT_RESET 4
#define HUB_PORT_POWER 8
#define HUB_PORT_LOW_SPEED 9
#define HUB_C_PORT_CONNECTION 16
#define HUB_C_PORT_ENABLE 17
#define HUB_C_PORT_SUSPEND 18
#define HUB_C_PORT_OVER_CURRENT 19
#define HUB_C_PORT_RESET 20
#endif
/* USB HID Class Request Code */
#ifndef HID_GET_REPORT
#define HID_GET_REPORT 0x01
#define HID_GET_IDLE 0x02
#define HID_GET_PROTOCOL 0x03
#define HID_SET_REPORT 0x09
#define HID_SET_IDLE 0x0A
#define HID_SET_PROTOCOL 0x0B
#endif
/* USB UDisk */
#ifndef USB_BO_CBW_SIZE
#define USB_BO_CBW_SIZE 0x1F
#define USB_BO_CSW_SIZE 0x0D
#endif
#ifndef USB_BO_CBW_SIG0
#define USB_BO_CBW_SIG0 0x55
#define USB_BO_CBW_SIG1 0x53
#define USB_BO_CBW_SIG2 0x42
#define USB_BO_CBW_SIG3 0x43
#define USB_BO_CSW_SIG0 0x55
#define USB_BO_CSW_SIG1 0x53
#define USB_BO_CSW_SIG2 0x42
#define USB_BO_CSW_SIG3 0x53
#endif
/* USB CDC Class request code */
#ifndef CDC_GET_LINE_CODING
#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */
#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */
#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */
#endif
/*******************************************************************************/
/* USBFS Related Register Macro Definition */
/* R8_USB_CTRL */
#define USBFS_UC_HOST_MODE 0x80
#define USBFS_UC_LOW_SPEED 0x40
#define USBFS_UC_DEV_PU_EN 0x20
#define USBFS_UC_SYS_CTRL_MASK 0x30
#define USBFS_UC_SYS_CTRL0 0x00
#define USBFS_UC_SYS_CTRL1 0x10
#define USBFS_UC_SYS_CTRL2 0x20
#define USBFS_UC_SYS_CTRL3 0x30
#define USBFS_UC_INT_BUSY 0x08
#define USBFS_UC_RESET_SIE 0x04
#define USBFS_UC_CLR_ALL 0x02
#define USBFS_UC_DMA_EN 0x01
/* R8_USB_INT_EN */
#define USBFS_UIE_DEV_SOF 0x80
#define USBFS_UIE_DEV_NAK 0x40
#define USBFS_UIE_FIFO_OV 0x10
#define USBFS_UIE_HST_SOF 0x08
#define USBFS_UIE_SUSPEND 0x04
#define USBFS_UIE_TRANSFER 0x02
#define USBFS_UIE_DETECT 0x01
#define USBFS_UIE_BUS_RST 0x01
/* R8_USB_DEV_AD */
#define USBFS_UDA_GP_BIT 0x80
#define USBFS_USB_ADDR_MASK 0x7F
/* R8_USB_MIS_ST */
#define USBFS_UMS_SOF_PRES 0x80
#define USBFS_UMS_SOF_ACT 0x40
#define USBFS_UMS_SIE_FREE 0x20
#define USBFS_UMS_R_FIFO_RDY 0x10
#define USBFS_UMS_BUS_RESET 0x08
#define USBFS_UMS_SUSPEND 0x04
#define USBFS_UMS_DM_LEVEL 0x02
#define USBFS_UMS_DEV_ATTACH 0x01
/* R8_USB_INT_FG */
#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
/* R8_USB_INT_ST */
#define USBFS_SETUP_ACT 0x80 // RO, indicate current USB transfer SETUP is complete
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
#define USBFS_UIS_TOKEN_OUT 0x00
#define USBFS_UIS_TOKEN_SOF 0x10
#define USBFS_UIS_TOKEN_IN 0x20
#define USBFS_UIS_TOKEN_SETUP 0x30
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
// 00: OUT token PID received
// 01: SOF token PID received
// 10: IN token PID received
// 11: SETUP token PID received
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
/* R8_UDEV_CTRL */
#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
#define USBFS_UD_GP_BIT 0x02 // general purpose bit
#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
/* R8_UEP4_1_MOD */
#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
// 0 0 x: disable endpoint and disable buffer
// 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
// 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
#define USBFS_UEP4_BUF_MOD 0x01
/* R8_UEP2_3_MOD */
#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
/* R8_UEP567_MOD */
#define USBFS_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT)
#define USBFS_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN)
#define USBFS_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT)
#define USBFS_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN)
#define USBFS_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT)
#define USBFS_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN)
/* R8_UEPn_TX_CTRL */
#define USBFS_UEP_T_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
#define USBFS_UEP_T_TOG (1<<6) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
#define USBFS_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
#define USBFS_UEP_T_RES_ACK (0<<1)
#define USBFS_UEP_T_RES_NONE (1<<0)
#define USBFS_UEP_T_RES_NAK (1<<1)
#define USBFS_UEP_T_RES_STALL (3<<0)
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
// 00: DATA0 or DATA1 then expecting ACK (ready)
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: STALL (error)
// host aux setup
/* R8_UEPn_RX_CTRL, n=0-7 */
#define USBFS_UEP_R_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
#define USBFS_UEP_R_TOG (1<<7) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
#define USBFS_UEP_R_RES_MASK (3<<2) // bit mask of handshake response type for USB endpoint X receiving (OUT)
#define USBFS_UEP_R_RES_ACK (0<<3)
#define USBFS_UEP_R_RES_NONE (1<<2)
#define USBFS_UEP_R_RES_NAK (1<<3)
#define USBFS_UEP_R_RES_STALL (3<<2)
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
// 00: ACK (ready)
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
// 10: NAK (busy)
// 11: STALL (error)
/* R8_UHOST_CTRL */
#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
/* R32_UH_EP_MOD */
#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
// 0 x: disable endpoint and disable buffer
// 1 0: 64 bytes buffer for receiving (IN endpoint)
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
/* R8_UH_SETUP */
#define USBFS_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub
#define USBFS_UH_SOF_EN 0x40 // USB host automatic SOF enable
/* R8_UH_EP_PID */
#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer
#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer
/* R8_UH_RX_CTRL */
#define USBFS_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define USBFS_UH_R_TOG (1<<7) // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
/* R8_UH_TX_CTRL */
#define USBFS_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
#define USBFS_UH_T_TOG (1<<6) // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
/*******************************************************************************/
/* Struct Definition */
/* USB Setup Request */
typedef struct __attribute__((packed)) _USB_SETUP_REQ
{
uint8_t bRequestType;
uint8_t bRequest;
uint16_t wValue;
uint16_t wIndex;
uint16_t wLength;
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
/* USB Device Descriptor */
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
/* USB Configuration Descriptor */
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t MaxPower;
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
/* USB Interface Descriptor */
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
/* USB Endpoint Descriptor */
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint8_t wMaxPacketSizeL;
uint8_t wMaxPacketSizeH;
uint8_t bInterval;
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
/* USB Configuration Descriptor Set */
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
{
USB_CFG_DESCR cfg_descr;
USB_ITF_DESCR itf_descr;
USB_ENDP_DESCR endp_descr[ 1 ];
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
/* USB HUB Descriptor */
typedef struct __attribute__((packed)) _USB_HUB_DESCR
{
uint8_t bDescLength;
uint8_t bDescriptorType;
uint8_t bNbrPorts;
uint8_t wHubCharacteristicsL;
uint8_t wHubCharacteristicsH;
uint8_t bPwrOn2PwrGood;
uint8_t bHubContrCurrent;
uint8_t DeviceRemovable;
uint8_t PortPwrCtrlMask;
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
/* USB HID Descriptor */
typedef struct __attribute__((packed)) _USB_HID_DESCR
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdHID;
uint8_t bCountryCode;
uint8_t bNumDescriptors;
uint8_t bDescriptorTypeX;
uint8_t wDescriptorLengthL;
uint8_t wDescriptorLengthH;
} USB_HID_DESCR, *PUSB_HID_DESCR;
/* USB UDisk */
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
{
uint32_t mCBW_Sig;
uint32_t mCBW_Tag;
uint32_t mCBW_DataLen;
uint8_t mCBW_Flag;
uint8_t mCBW_LUN;
uint8_t mCBW_CB_Len;
uint8_t mCBW_CB_Buf[ 16 ];
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
/* USB UDisk */
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
{
uint32_t mCBW_Sig;
uint32_t mCBW_Tag;
uint32_t mCSW_Residue;
uint8_t mCSW_Status;
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
#ifdef __cplusplus
}
#endif
#endif /*__CH32X035_USB_H */

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_usbpd.h
* Author : WCH
* Version : V1.0.0
* Date : 2023/04/06
* Description : This file contains all the functions prototypes for the USBPD
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32X035_USBPD_H
#define __CH32X035_USBPD_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32x035.h"
#ifndef VOID
#define VOID void
#endif
#ifndef CONST
#define CONST const
#endif
#ifndef BOOL
typedef unsigned char BOOL;
#endif
#ifndef BOOLEAN
typedef unsigned char BOOLEAN;
#endif
#ifndef CHAR
typedef char CHAR;
#endif
#ifndef INT8
typedef char INT8;
#endif
#ifndef INT16
typedef short INT16;
#endif
#ifndef INT32
typedef long INT32;
#endif
#ifndef UINT8
typedef unsigned char UINT8;
#endif
#ifndef UINT16
typedef unsigned short UINT16;
#endif
#ifndef UINT32
typedef unsigned long UINT32;
#endif
#ifndef UINT8V
typedef unsigned char volatile UINT8V;
#endif
#ifndef UINT16V
typedef unsigned short volatile UINT16V;
#endif
#ifndef UINT32V
typedef unsigned long volatile UINT32V;
#endif
#ifndef PVOID
typedef void *PVOID;
#endif
#ifndef PCHAR
typedef char *PCHAR;
#endif
#ifndef PCHAR
typedef const char *PCCHAR;
#endif
#ifndef PINT8
typedef char *PINT8;
#endif
#ifndef PINT16
typedef short *PINT16;
#endif
#ifndef PINT32
typedef long *PINT32;
#endif
#ifndef PUINT8
typedef unsigned char *PUINT8;
#endif
#ifndef PUINT16
typedef unsigned short *PUINT16;
#endif
#ifndef PUINT32
typedef unsigned long *PUINT32;
#endif
#ifndef PUINT8V
typedef volatile unsigned char *PUINT8V;
#endif
#ifndef PUINT16V
typedef volatile unsigned short *PUINT16V;
#endif
#ifndef PUINT32V
typedef volatile unsigned long *PUINT32V;
#endif
/******************************************************************************/
/* Related macro definitions */
/* Define the return value of the function */
#ifndef SUCCESS
#define SUCCESS 0
#endif
#ifndef FAIL
#define FAIL 0xFF
#endif
/* Register Bit Definition */
/* USBPD->CONFIG */
#define PD_FILT_ED (1<<0) /* PD pin input filter enable */
#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */
#define CC_SEL (1<<2) /* Select PD communication port */
#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */
#define PD_RST_EN (1<<4) /* PD mode reset command enable */
#define WAKE_POLAR (1<<5) /* PD port wake-up level */
#define IE_PD_IO (1<<10) /* PD IO interrupt enable */
#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */
#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */
#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */
#define IE_RX_RESET (1<<14) /* Reset interrupt enable */
#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */
/* USBPD->CONTROL */
#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */
#define BMC_START (1<<1) /* BMC send start signal */
#define RX_STATE_0 (1<<2) /* PD received state bit 0 */
#define RX_STATE_1 (1<<3) /* PD received state bit 1 */
#define RX_STATE_2 (1<<4) /* PD received state bit 2 */
#define DATA_FLAG (1<<5) /* Cache data valid flag bit */
#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */
#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */
/* USBPD->TX_SEL */
#define TX_SEL1 (0<<0)
#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */
#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */
#define TX_SEL2_Mask (3<<2)
#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */
#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */
#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */
#define TX_SEL3_Mask (3<<4)
#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */
#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */
#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */
#define TX_SEL4_Mask (3<<6)
#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */
#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */
#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */
/* USBPD->STATUS */
#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */
#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */
#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */
#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */
#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */
#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */
#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */
#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */
#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */
#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */
#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */
/* USBPD->PORT_CC1 */
/* USBPD->PORT_CC2 */
#define PA_CC_AI (1<<0) /* CC port comparator analogue input */
#define CC_PD (1<<1) /* CC port pull-down resistor enable */
#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */
#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */
#define CC_PU_330 (1<<2) /* 01-330uA */
#define CC_PU_180 (2<<2) /* 10-180uA */
#define CC_PU_80 (3<<2) /* 11-80uA */
#define CC_LVE (1<<4) /* CC port output low voltage enable */
#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/
#define CC_NO_CMP (0<<5) /* 000-closed */
#define CC_CMP_22 (2<<5) /* 010-0.22V */
#define CC_CMP_45 (3<<5) /* 011-0.45V */
#define CC_CMP_55 (4<<5) /* 100-0.55V */
#define CC_CMP_66 (5<<5) /* 101-0.66V */
#define CC_CMP_95 (6<<5) /* 110-0.95V */
#define CC_CMP_123 (7<<5) /* 111-1.23V */
#define USBPD_IN_HVT (1<<9)
/*********************************************************
* PD pin PC14/PC15 high threshold input mode:
* 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication
* 0-Normal GPIO threshold input
* *******************************************************/
#define USBPD_PHY_V33 (1<<8)
/**********************************************************
* PD transceiver PHY pull-up limit configuration bits:
* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V
* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V
* ********************************************************/
/* Control Message Types */
#define DEF_TYPE_RESERVED 0x00
#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */
#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_PING 0x05 /* Send By: Source */
#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */
#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */
#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */
#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */
#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */
#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */
#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */
#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */
#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */
#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */
#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */
#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */
#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */
#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */
#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */
#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */
/* Data Message Types */
#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */
#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */
#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */
#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */
#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */
#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */
#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */
#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */
#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */
#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */
#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */
#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */
/* Vendor Define Message Command */
#define DEF_VDM_DISC_IDENT 0x01
#define DEF_VDM_DISC_SVID 0x02
#define DEF_VDM_DISC_MODE 0x03
#define DEF_VDM_ENTER_MODE 0x04
#define DEF_VDM_EXIT_MODE 0x05
#define DEF_VDM_ATTENTION 0x06
#define DEF_VDM_DP_S_UPDATE 0x10
#define DEF_VDM_DP_CONFIG 0x11
/* PD Revision */
#define DEF_PD_REVISION_10 0x00
#define DEF_PD_REVISION_20 0x01
#define DEF_PD_REVISION_30 0x02
/* PD PHY Channel */
#define DEF_PD_CC1 0x00
#define DEF_PD_CC2 0x01
#define PIN_CC1 GPIO_Pin_14
#define PIN_CC2 GPIO_Pin_15
/* PD Tx Status */
#define DEF_PD_TX_OK 0x00
#define DEF_PD_TX_FAIL 0x01
/* PDO INDEX */
#define PDO_INDEX_1 1
#define PDO_INDEX_2 2
#define PDO_INDEX_3 3
#define PDO_INDEX_4 4
#define PDO_INDEX_5 5
/******************************************************************************/
#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */
#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */
#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */
#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */
#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */
#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */
#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */
#define PD_RX_SOP0 0x01 /* SOP0 received */
#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */
#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */
#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */
#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */
#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */
#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/
#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/
#define bCC_CMP_22 0X01
#define bCC_CMP_45 0X02
#define bCC_CMP_55 0X04
#define bCC_CMP_66 0X08
#define bCC_CMP_95 0X10
#define bCC_CMP_123 0X20
#define bCC_CMP_220 0X40
/******************************************************************************/
/* PD State Machine */
typedef enum
{
STA_IDLE = 0, /* 0: No task status */
STA_DISCONNECT, /* 1: Disconnection */
STA_SRC_CONNECT, /* 2: SRC connect */
STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */
STA_RX_SRC_CAP, /* 4: SRC_CAP received */
STA_TX_REQ, /* 5: Send REQUEST */
STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */
STA_RX_ACCEPT, /* 7: ACCEPT received */
STA_RX_REJECT, /* 8: REJECT received */
STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */
STA_RX_PS_RDY, /* 10: PS_RDY received */
STA_SINK_CONNECT, /* 11: SNK access */
STA_TX_SRC_CAP, /* 12: Send SRC_CAP */
STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */
STA_RX_REQ, /* 14: REQUEST received */
STA_TX_ACCEPT, /* 15: Send ACCEPT */
STA_TX_REJECT, /* 16: Send REJECT */
STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */
STA_TX_PS_RDY, /* 18: Send PS_RDY */
STA_TX_DR_SWAP, /* 19: Send DR_SWAP */
STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */
STA_TX_PR_SWAP, /* 21: Send PR_SWAP */
STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */
STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */
STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */
STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */
STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */
STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */
STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */
STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */
STA_MODE_SWITCH, /* 30: Mode switching */
STA_TX_SOFTRST, /* 31: Sending a software reset */
STA_TX_HRST, /* 32: Send hardware reset */
STA_PHY_RST, /* 33: PHY reset */
STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */
} CC_STATUS;
/******************************************************************************/
/* PD Message Header Struct */
typedef union
{
struct _Message_Header
{
UINT8 MsgType: 5; /* Message Type */
UINT8 PDRole: 1; /* 0-UFP; 1-DFP */
UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */
UINT8 PRRole: 1; /* 0-Sink; 1-Source */
UINT8 MsgID: 3;
UINT8 NumDO: 3;
UINT8 Ext: 1;
}Message_Header;
UINT16 Data;
}_Message_Header;
/******************************************************************************/
/* Bit definition */
typedef union
{
struct _BITS_
{
UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */
UINT8 Connected: 1; /* PD Physical Layer Connected Flag */
UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */
UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */
UINT8 PR_Role: 1; /* 0-Sink; 1-Source */
UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */
UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */
UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */
UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */
UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */
UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */
UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */
UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */
UINT8 Recv: 3;
}Bit;
UINT16 Bit_Flag;
}_BIT_FLAG;
/* PD control-related structures */
typedef struct _PD_CONTROL
{
CC_STATUS PD_State; /* PD communication status machine */
CC_STATUS PD_State_Last; /* PD communication status machine (last value) */
UINT8 Msg_ID; /* ID of the message sent */
UINT8 Det_Timer; /* PD connection status detection timing */
UINT8 Det_Cnt; /* Number of PD connection status detections */
UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */
UINT8 HPD_Det_Timer; /* HPD connection detection timing */
UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */
UINT16 PD_Comm_Timer; /* PD shared timing variables */
UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */
UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */
UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */
UINT8 Err_Op_Cnt; /* Exception operation count */
UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */
_BIT_FLAG Flag; /* Flag byte bit definition */
}PD_CONTROL, *pPD_CONTROL;
#ifdef __cplusplus
}
#endif
#endif

299
Peripheral/src/ch32x035_flash.c
View File

@ -2,7 +2,7 @@
* File Name : ch32x035_flash.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/04/06
* Date : 2023/11/23
* Description : This file provides all the FLASH firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@ -28,6 +28,7 @@
#define CR_FLOCK_Set ((uint32_t)0x00008000)
#define CR_PAGE_PG ((uint32_t)0x00010000)
#define CR_PAGE_ER ((uint32_t)0x00020000)
#define CR_PAGE_ER_Reset ((uint32_t)0xFFFDFFFF)
#define CR_BUF_LOAD ((uint32_t)0x00040000)
#define CR_BUF_RST ((uint32_t)0x00080000)
#define CR_BER32 ((uint32_t)0x00800000)
@ -56,6 +57,15 @@
#define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00005000)
/* Flash Program Vaild Address */
#define ValidAddrStart (FLASH_BASE)
#define ValidAddrEnd (FLASH_BASE + 0xF800)
/* FLASH Size */
#define Size_256B 0x100
#define Size_1KB 0x400
#define Size_32KB 0x8000
/********************************************************************************
* @fn FLASH_SetLatency
*
@ -122,6 +132,7 @@ FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
if(status == FLASH_COMPLETE)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
FLASH->CTLR |= CR_PER_Set;
FLASH->ADDR = Page_Address;
FLASH->CTLR |= CR_STRT_Set;
@ -149,6 +160,7 @@ FLASH_Status FLASH_EraseAllPages(void)
status = FLASH_WaitForLastOperation(EraseTimeout);
if(status == FLASH_COMPLETE)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
FLASH->CTLR |= CR_MER_Set;
FLASH->CTLR |= CR_STRT_Set;
@ -180,6 +192,7 @@ FLASH_Status FLASH_EraseOptionBytes(void)
FLASH->OBKEYR = FLASH_KEY1;
FLASH->OBKEYR = FLASH_KEY2;
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
FLASH->CTLR |= CR_OPTER_Set;
FLASH->CTLR |= CR_STRT_Set;
status = FLASH_WaitForLastOperation(EraseTimeout);
@ -631,6 +644,8 @@ void FLASH_Lock_Fast(void)
*/
void FLASH_BufReset(void)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
FLASH->CTLR |= CR_PAGE_PG;
FLASH->CTLR |= CR_BUF_RST;
while(FLASH->STATR & SR_BSY)
@ -650,6 +665,8 @@ void FLASH_BufReset(void)
*/
void FLASH_BufLoad(uint32_t Address, uint32_t Data0)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
FLASH->CTLR |= CR_PAGE_PG;
*(__IO uint32_t *)(Address) = Data0;
FLASH->CTLR |= CR_BUF_LOAD;
@ -669,6 +686,8 @@ void FLASH_BufLoad(uint32_t Address, uint32_t Data0)
*/
void FLASH_ErasePage_Fast(uint32_t Page_Address)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
FLASH->CTLR |= CR_PAGE_ER;
FLASH->ADDR = Page_Address;
FLASH->CTLR |= CR_STRT_Set;
@ -688,6 +707,8 @@ void FLASH_ErasePage_Fast(uint32_t Page_Address)
*/
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
Block_Address &= 0xFFFF8000;
FLASH->CTLR |= CR_BER32;
@ -709,6 +730,8 @@ void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address)
*/
void FLASH_ProgramPage_Fast(uint32_t Page_Address)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
FLASH->CTLR |= CR_PAGE_PG;
FLASH->ADDR = Page_Address;
FLASH->CTLR |= CR_STRT_Set;
@ -741,3 +764,277 @@ void SystemReset_StartMode(uint32_t Mode)
FLASH_Lock();
}
/*********************************************************************
* @fn ROM_ERASE
*
* @brief Select erases a specified FLASH .
*
* @param StartAddr - Erases Flash start address(StartAddr%256 == 0).
* Cnt - Erases count.
* Erase_Size - Erases size select.The returned value can be:
* Size_32KB, Size_1KB, Size_256B.
*
* @return none.
*/
static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size)
{
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
do{
if(Erase_Size == Size_32KB)
{
FLASH->CTLR |= CR_BER32;
}
else if(Erase_Size == Size_1KB)
{
FLASH->CTLR |= CR_PER_Set;
}
else if(Erase_Size == Size_256B)
{
FLASH->CTLR |= CR_PAGE_ER;
}
FLASH->ADDR = StartAddr;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
if(Erase_Size == Size_32KB)
{
FLASH->CTLR &= ~CR_BER32;
StartAddr += Size_32KB;
}
else if(Erase_Size == Size_1KB)
{
FLASH->CTLR &= ~CR_PER_Set;
StartAddr += Size_1KB;
}
else if(Erase_Size == Size_256B)
{
FLASH->CTLR &= ~CR_PAGE_ER;
StartAddr += Size_256B;
}
}while(--Cnt);
}
/*********************************************************************
* @fn FLASH_ROM_ERASE
*
* @brief Erases a specified FLASH .
*
* @param StartAddr - Erases Flash start address(StartAddr%256 == 0).
* Length - Erases Flash start Length(Length%256 == 0).
*
* @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR,
* FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE.
*/
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length)
{
uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0;
FLASH_Status status = FLASH_COMPLETE;
if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd))
{
return FLASH_ADR_RANGE_ERROR;
}
if((StartAddr + Length) > ValidAddrEnd)
{
return FLASH_OP_RANGE_ERROR;
}
if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0))
{
return FLASH_ALIGN_ERROR;
}
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
/* Fast mode unlock */
FLASH->MODEKEYR = FLASH_KEY1;
FLASH->MODEKEYR = FLASH_KEY2;
Addr0 = StartAddr;
if(Length >= Size_32KB)
{
Length0 = Size_32KB - (Addr0 & (Size_32KB - 1));
Addr1 = StartAddr + Length0;
Length1 = Length - Length0;
}
else if(Length >= Size_1KB)
{
Length0 = Size_1KB - (Addr0 & (Size_1KB - 1));
Addr1 = StartAddr + Length0;
Length1 = Length - Length0;
}
else if(Length >= Size_256B)
{
Length0 = Length;
}
/* Erase 32KB */
if(Length0 >= Size_32KB)//front
{
Length = Length0;
if(Addr0 & (Size_32KB - 1))
{
Length0 = Size_32KB - (Addr0 & (Size_32KB - 1));
}
else
{
Length0 = 0;
}
ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB);
}
if(Length1 >= Size_32KB)//back
{
StartAddr = Addr1;
Length = Length1;
if((Addr1 + Length1) & (Size_32KB - 1))
{
Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1)));
Length1 = (StartAddr + Length1) & (Size_32KB - 1);
}
else
{
Length1 = 0;
}
ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB);
}
/* Erase 1KB */
if(Length0 >= Size_1KB) //front
{
Length = Length0;
if(Addr0 & (Size_1KB - 1))
{
Length0 = Size_1KB - (Addr0 & (Size_1KB - 1));
}
else
{
Length0 = 0;
}
ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB);
}
if(Length1 >= Size_1KB) //back
{
StartAddr = Addr1;
Length = Length1;
if((Addr1 + Length1) & (Size_1KB - 1))
{
Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1)));
Length1 = (StartAddr + Length1) & (Size_1KB - 1);
}
else
{
Length1 = 0;
}
ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB);
}
/* Erase 256B */
if(Length0)//front
{
ROM_ERASE(Addr0, (Length0 >> 8), Size_256B);
}
if(Length1)//back
{
ROM_ERASE(Addr1, (Length1 >> 8), Size_256B);
}
FLASH->CTLR |= CR_FLOCK_Set;
FLASH->CTLR |= CR_LOCK_Set;
return status;
}
/*********************************************************************
* @fn FLASH_ROM_WRITE
*
* @brief Writes a specified FLASH .
*
* @param StartAddr - Writes Flash start address(StartAddr%256 == 0).
* Length - Writes Flash start Length(Length%256 == 0).
* pbuf - Writes Flash value buffer.
*
* @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR,
* FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE.
*/
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length)
{
uint32_t i, adr;
uint8_t size;
FLASH_Status status = FLASH_COMPLETE;
if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd))
{
return FLASH_ADR_RANGE_ERROR;
}
if((StartAddr + Length) > ValidAddrEnd)
{
return FLASH_OP_RANGE_ERROR;
}
if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0))
{
return FLASH_ALIGN_ERROR;
}
adr = StartAddr;
i = Length >> 8;
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
/* Fast program mode unlock */
FLASH->MODEKEYR = FLASH_KEY1;
FLASH->MODEKEYR = FLASH_KEY2;
FLASH->CTLR &= (CR_OPTER_Reset & CR_PAGE_ER_Reset);
do{
FLASH->CTLR |= CR_PAGE_PG;
FLASH->CTLR |= CR_BUF_RST;
while(FLASH->STATR & SR_BSY)
;
size = 64;
while(size)
{
*(uint32_t *)StartAddr = *(uint32_t *)pbuf;
FLASH->CTLR |= CR_BUF_LOAD;
while(FLASH->STATR & SR_BSY)
;
StartAddr += 4;
pbuf += 1;
size -= 1;
}
FLASH->ADDR = adr;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_PAGE_PG;
adr += 256;
}while(--i);
FLASH->CTLR |= CR_FLOCK_Set;
FLASH->CTLR |= CR_LOCK_Set;
return status;
}

24
Peripheral/src/ch32x035_gpio.c
View File

@ -2,7 +2,7 @@
* File Name : ch32x035_gpio.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/04/06
* Date : 2023/11/06
* Description : This file provides all the GPIO firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
@ -326,15 +326,8 @@ uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
*/
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00)
{
GPIOx->BSHR = GPIO_Pin;
}
if(GPIO_Pin > 0x00FFFF)
{
GPIOx->BSXR = (GPIO_Pin>>0x10);
}
GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF);
GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10);
}
/*********************************************************************
@ -370,15 +363,8 @@ void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal)
{
if(BitVal != Bit_RESET)
{
if((GPIO_Pin & ((uint32_t)0x00FFFF)) != 0x00)
{
GPIOx->BSHR = GPIO_Pin;
}
if(GPIO_Pin > 0x00FFFF)
{
GPIOx->BSXR = (GPIO_Pin>>0x10);
}
GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF);
GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10);
}
else
{