diff --git a/.clang-format b/.clang-format
new file mode 100644
index 0000000..fd84a72
--- /dev/null
+++ b/.clang-format
@@ -0,0 +1,12 @@
+BasedOnStyle: Google
+IndentWidth: 4
+AlignConsecutiveMacros: AcrossEmptyLines
+AlignConsecutiveDeclarations: Consecutive
+AlignConsecutiveAssignments: Consecutive
+AllowShortFunctionsOnASingleLine: None
+BreakBeforeBraces: Custom
+BraceWrapping:
+ AfterEnum: false
+ AfterStruct: false
+ SplitEmptyFunction: false
+ColumnLimit: 120
\ No newline at end of file
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 0251e8f..3e10576 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,6 +1,6 @@
cmake_minimum_required(VERSION 3.10)
-project(lpcxpresso_55s69_template)
+project(lpcxpresso_55s69_spo2)
enable_language(CXX)
enable_language(ASM)
@@ -60,6 +60,7 @@ set(TARGET_SOURCES
"board/clock_config.c"
"board/peripherals.c"
"board/pin_mux.c"
+ "src/afe_impl.c"
"src/main.c"
)
@@ -85,6 +86,7 @@ set(TARGET_C_INCLUDES
# Shared libraries linked with application
set(TARGET_LIBS
+ "afe44x0"
"c"
"m"
"nosys"
@@ -113,6 +115,8 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wall -fno-common -fno-builtin -f
set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp")
set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -Wl,--gc-sections")
+add_subdirectory(lib/afe44x0)
+
# Shared sources, includes and definitions
add_compile_definitions(${TARGET_C_DEFINES})
include_directories(${TARGET_C_INCLUDES})
diff --git a/LPCXpresso55S69.mex b/LPCXpresso55S69.mex
index 5bc9c26..0d53068 100644
--- a/LPCXpresso55S69.mex
+++ b/LPCXpresso55S69.mex
@@ -27,6 +27,13 @@
12.0.0
+
+
+
+
+
+
+
@@ -290,6 +297,7 @@
+
@@ -516,6 +524,64 @@
+
+ Configures pin routing and optionally pin electrical features.
+
+ true
+ cm33_core0
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
@@ -748,12 +814,14 @@
+
+
diff --git a/SDK b/SDK
new file mode 160000
index 0000000..4426225
--- /dev/null
+++ b/SDK
@@ -0,0 +1 @@
+Subproject commit 442622515005ffb9fd32e59d3fbd470f0f67550b
diff --git a/board/clock_config.c b/board/clock_config.c
index 5f21ddd..f94dd79 100644
--- a/board/clock_config.c
+++ b/board/clock_config.c
@@ -217,11 +217,13 @@ void BOARD_BootClockPLL100M(void)
name: BOARD_BootClockPLL150M
called_from_default_init: true
outputs:
+- {id: HSLSPI_clock.outFreq, value: 150 MHz}
- {id: System_clock.outFreq, value: 150 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: ENABLE_CLKIN_ENA, value: Enabled}
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
+- {id: SYSCON.HSLSPICLKSEL.sel, value: SYSCON.MAINCLKSELB}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
@@ -276,6 +278,7 @@ void BOARD_BootClockPLL150M(void)
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
+ CLOCK_AttachClk(kMAIN_CLK_to_HSLSPI); /*!< Switch HSLSPI to MAIN_CLK */
/*!< Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
diff --git a/board/pin_mux.c b/board/pin_mux.c
index 1c8f15c..844667e 100644
--- a/board/pin_mux.c
+++ b/board/pin_mux.c
@@ -13,6 +13,14 @@ package_id: LPC55S69JBD100
mcu_data: ksdk2_0
processor_version: 12.0.0
board: LPCXpresso55S69
+pin_labels:
+- {pin_num: '14', pin_signal: PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8, label: 'P19[2]/P23[1]/ADC0_N', identifier: LED_ALM}
+- {pin_num: '27', pin_signal: PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27, label: 'P18[13]/P24[4]/FC2_USART_TXD_ARD',
+ identifier: PD_ALM}
+- {pin_num: '31', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0, label: 'P17[17]/P24[1]/PIO1_5_GPIO_ARD', identifier: AFE_PDN}
+- {pin_num: '64', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, label: 'S2/P18[16]/P24[2]/WAKE/GPIO', identifier: S2;ADC_RDY}
+- {pin_num: '3', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6, label: 'P18[15]/P18[10]/P24[3]/PLU_OUT6/GPIO/FC2_USART_RXD_ARD/SD1_D1',
+ identifier: DIAG_END}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
*/
/* clang-format on */
@@ -32,6 +40,7 @@ void BOARD_InitBootPins(void)
{
BOARD_InitDEBUG_UARTPins();
BOARD_InitPins_Core0();
+ BOARD_InitSPO2Pins();
}
/* clang-format off */
@@ -443,7 +452,7 @@ BOARD_InitBUTTONsPins:
- pin_list:
- {pin_num: '88', peripheral: GPIO, signal: 'PIO0, 5', pin_signal: PIO0_5/FC4_RXD_SDA_MOSI_DATA/CTIMER3_MAT0/SCT_GPI5/FC3_RTS_SCL_SSEL1/MCLK/SECURE_GPIO0_5, direction: INPUT,
mode: pullUp, slew_rate: standard, invert: disabled, open_drain: disabled}
- - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, direction: INPUT, mode: pullUp, slew_rate: standard,
+ - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, identifier: S2, direction: INPUT, mode: pullUp, slew_rate: standard,
invert: disabled, open_drain: disabled}
- {pin_num: '10', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC1_SCK/CT_INP4/SCT0_OUT2/FC4_CTS_SDA_SSEL0/ADC0_12, direction: INPUT, mode: pullUp, slew_rate: standard,
invert: disabled, open_drain: disabled, asw: enabled}
@@ -845,6 +854,197 @@ void BOARD_InitACCELPins(void)
/* PORT1 PIN21 (coords: 30) is configured as FC4_RXD_SDA_MOSI_DATA */
IOCON_PinMuxSet(IOCON, BOARD_INITACCELPINS_FC4_I2C_SDA_PORT, BOARD_INITACCELPINS_FC4_I2C_SDA_PIN, FC4_I2C_SDA);
}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitSPO2Pins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: '62', peripheral: FLEXCOMM8, signal: HS_SPI_MISO, pin_signal: PIO1_3/SCT0_OUT4/HS_SPI_MISO/USB0_PORTPWRN/PLU_OUT6}
+ - {pin_num: '60', peripheral: FLEXCOMM8, signal: HS_SPI_MOSI, pin_signal: PIO0_26/FC2_RXD_SDA_MOSI_DATA/CLKOUT/CT_INP14/SCT0_OUT5/USB0_IDVALUE/FC0_SCK/HS_SPI_MOSI/SECURE_GPIO0_26}
+ - {pin_num: '61', peripheral: FLEXCOMM8, signal: HS_SPI_SCK, pin_signal: PIO1_2/CTIMER0_MAT3/SCT_GPI6/HS_SPI_SCK/USB1_PORTPWRN/PLU_OUT5}
+ - {pin_num: '59', peripheral: FLEXCOMM8, signal: HS_SPI_SSEL1, pin_signal: PIO1_1/FC3_RXD_SDA_MOSI_DATA/CT_INP3/SCT_GPI5/HS_SPI_SSEL1/USB1_OVERCURRENTN/PLU_OUT4}
+ - {pin_num: '31', peripheral: GPIO, signal: 'PIO1, 5', pin_signal: PIO1_5/FC0_RXD_SDA_MOSI_DATA/SD0_D2/CTIMER2_MAT0/SCT_GPI0, direction: OUTPUT, gpio_init_state: 'true'}
+ - {pin_num: '64', peripheral: GPIO, signal: 'PIO1, 18', pin_signal: PIO1_18/SD1_POW_EN/SCT0_OUT5/PLU_OUT0, identifier: ADC_RDY, direction: INPUT}
+ - {pin_num: '3', peripheral: GPIO, signal: 'PIO1, 24', pin_signal: PIO1_24/FC2_RXD_SDA_MOSI_DATA/SCT0_OUT1/SD1_D1/FC3_SSEL3/PLU_OUT6, direction: INPUT}
+ - {pin_num: '27', peripheral: GPIO, signal: 'PIO0, 27', pin_signal: PIO0_27/FC2_TXD_SCL_MISO_WS/CTIMER3_MAT2/SCT0_OUT6/FC7_RXD_SDA_MOSI_DATA/PLU_OUT0/SECURE_GPIO0_27,
+ direction: INPUT}
+ - {pin_num: '14', peripheral: GPIO, signal: 'PIO0, 16', pin_signal: PIO0_16/FC4_TXD_SCL_MISO_WS/CLKOUT/CT_INP4/SECURE_GPIO0_16/ADC0_8, direction: INPUT}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitSPO2Pins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+/* Function assigned for the Cortex-M33 (Core #0) */
+void BOARD_InitSPO2Pins(void)
+{
+ /* Enables the clock for the I/O controller.: Enable Clock. */
+ CLOCK_EnableClock(kCLOCK_Iocon);
+
+ /* Enables the clock for the GPIO0 module */
+ CLOCK_EnableClock(kCLOCK_Gpio0);
+
+ /* Enables the clock for the GPIO1 module */
+ CLOCK_EnableClock(kCLOCK_Gpio1);
+
+ gpio_pin_config_t LED_ALM_config = {
+ .pinDirection = kGPIO_DigitalInput,
+ .outputLogic = 0U
+ };
+ /* Initialize GPIO functionality on pin PIO0_16 (pin 14) */
+ GPIO_PinInit(BOARD_INITSPO2PINS_LED_ALM_GPIO, BOARD_INITSPO2PINS_LED_ALM_PORT, BOARD_INITSPO2PINS_LED_ALM_PIN, &LED_ALM_config);
+
+ gpio_pin_config_t PD_ALM_config = {
+ .pinDirection = kGPIO_DigitalInput,
+ .outputLogic = 0U
+ };
+ /* Initialize GPIO functionality on pin PIO0_27 (pin 27) */
+ GPIO_PinInit(BOARD_INITSPO2PINS_PD_ALM_GPIO, BOARD_INITSPO2PINS_PD_ALM_PORT, BOARD_INITSPO2PINS_PD_ALM_PIN, &PD_ALM_config);
+
+ gpio_pin_config_t AFE_PDN_config = {
+ .pinDirection = kGPIO_DigitalOutput,
+ .outputLogic = 1U
+ };
+ /* Initialize GPIO functionality on pin PIO1_5 (pin 31) */
+ GPIO_PinInit(BOARD_INITSPO2PINS_AFE_PDN_GPIO, BOARD_INITSPO2PINS_AFE_PDN_PORT, BOARD_INITSPO2PINS_AFE_PDN_PIN, &AFE_PDN_config);
+
+ gpio_pin_config_t ADC_RDY_config = {
+ .pinDirection = kGPIO_DigitalInput,
+ .outputLogic = 0U
+ };
+ /* Initialize GPIO functionality on pin PIO1_18 (pin 64) */
+ GPIO_PinInit(BOARD_INITSPO2PINS_ADC_RDY_GPIO, BOARD_INITSPO2PINS_ADC_RDY_PORT, BOARD_INITSPO2PINS_ADC_RDY_PIN, &ADC_RDY_config);
+
+ gpio_pin_config_t DIAG_END_config = {
+ .pinDirection = kGPIO_DigitalInput,
+ .outputLogic = 0U
+ };
+ /* Initialize GPIO functionality on pin PIO1_24 (pin 3) */
+ GPIO_PinInit(BOARD_INITSPO2PINS_DIAG_END_GPIO, BOARD_INITSPO2PINS_DIAG_END_PORT, BOARD_INITSPO2PINS_DIAG_END_PIN, &DIAG_END_config);
+
+ IOCON->PIO[0][16] = ((IOCON->PIO[0][16] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT016 (pin 14) is configured as PIO0_16. */
+ | IOCON_PIO_FUNC(PIO0_16_FUNC_ALT0)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO0_16_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[0][26] = ((IOCON->PIO[0][26] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT026 (pin 60) is configured as HS_SPI_MOSI. */
+ | IOCON_PIO_FUNC(0x09u)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO0_26_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[0][27] = ((IOCON->PIO[0][27] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT027 (pin 27) is configured as PIO0_27. */
+ | IOCON_PIO_FUNC(PIO0_27_FUNC_ALT0)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO0_27_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[1][1] = ((IOCON->PIO[1][1] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT11 (pin 59) is configured as HS_SPI_SSEL1. */
+ | IOCON_PIO_FUNC(PIO1_1_FUNC_ALT5)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO1_1_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[1][18] = ((IOCON->PIO[1][18] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT118 (pin 64) is configured as PIO1_18. */
+ | IOCON_PIO_FUNC(PIO1_18_FUNC_ALT0)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO1_18_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[1][2] = ((IOCON->PIO[1][2] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT12 (pin 61) is configured as HS_SPI_SCK. */
+ | IOCON_PIO_FUNC(PIO1_2_FUNC_ALT6)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO1_2_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[1][24] = ((IOCON->PIO[1][24] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT124 (pin 3) is configured as PIO1_24. */
+ | IOCON_PIO_FUNC(PIO1_24_FUNC_ALT0)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO1_24_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[1][3] = ((IOCON->PIO[1][3] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT13 (pin 62) is configured as HS_SPI_MISO. */
+ | IOCON_PIO_FUNC(PIO1_3_FUNC_ALT6)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO1_3_DIGIMODE_DIGITAL));
+
+ IOCON->PIO[1][5] = ((IOCON->PIO[1][5] &
+ /* Mask bits to zero which are setting */
+ (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK)))
+
+ /* Selects pin function.
+ * : PORT15 (pin 31) is configured as PIO1_5. */
+ | IOCON_PIO_FUNC(PIO1_5_FUNC_ALT0)
+
+ /* Select Digital mode.
+ * : Enable Digital mode.
+ * Digital input is enabled. */
+ | IOCON_PIO_DIGIMODE(PIO1_5_DIGIMODE_DIGITAL));
+}
/***********************************************************************************************************************
* EOF
**********************************************************************************************************************/
diff --git a/board/pin_mux.h b/board/pin_mux.h
index 1678fa9..7195089 100644
--- a/board/pin_mux.h
+++ b/board/pin_mux.h
@@ -435,6 +435,119 @@ void BOARD_InitI2SPins(void); /* Function assigned for the Cortex-M33 (Core #0)
*/
void BOARD_InitACCELPins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_16_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_16_FUNC_ALT0 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_26_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO0_27_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO0_27_FUNC_ALT0 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_18_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO1_18_FUNC_ALT0 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_1_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 5. */
+#define PIO1_1_FUNC_ALT5 0x05u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_24_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO1_24_FUNC_ALT0 0x00u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_2_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 6. */
+#define PIO1_2_FUNC_ALT6 0x06u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_3_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 6. */
+#define PIO1_3_FUNC_ALT6 0x06u
+/*!
+ * @brief Select Digital mode.: Enable Digital mode. Digital input is enabled. */
+#define PIO1_5_DIGIMODE_DIGITAL 0x01u
+/*!
+ * @brief Selects pin function.: Alternative connection 0. */
+#define PIO1_5_FUNC_ALT0 0x00u
+
+/*! @name PIO1_5 (number 31), P17[17]/P24[1]/PIO1_5_GPIO_ARD
+ @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITSPO2PINS_AFE_PDN_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITSPO2PINS_AFE_PDN_GPIO_PIN_MASK (1U << 5U) /*!<@brief GPIO pin mask */
+#define BOARD_INITSPO2PINS_AFE_PDN_PORT 1U /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITSPO2PINS_AFE_PDN_PIN 5U /*!<@brief PORT pin number */
+#define BOARD_INITSPO2PINS_AFE_PDN_PIN_MASK (1U << 5U) /*!<@brief PORT pin mask */
+ /* @} */
+
+/*! @name PIO1_18 (number 64), S2/P18[16]/P24[2]/WAKE/GPIO
+ @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITSPO2PINS_ADC_RDY_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITSPO2PINS_ADC_RDY_GPIO_PIN_MASK (1U << 18U) /*!<@brief GPIO pin mask */
+#define BOARD_INITSPO2PINS_ADC_RDY_PORT 1U /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITSPO2PINS_ADC_RDY_PIN 18U /*!<@brief PORT pin number */
+#define BOARD_INITSPO2PINS_ADC_RDY_PIN_MASK (1U << 18U) /*!<@brief PORT pin mask */
+ /* @} */
+
+/*! @name PIO1_24 (number 3), P18[15]/P18[10]/P24[3]/PLU_OUT6/GPIO/FC2_USART_RXD_ARD/SD1_D1
+ @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITSPO2PINS_DIAG_END_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITSPO2PINS_DIAG_END_GPIO_PIN_MASK (1U << 24U) /*!<@brief GPIO pin mask */
+#define BOARD_INITSPO2PINS_DIAG_END_PORT 1U /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITSPO2PINS_DIAG_END_PIN 24U /*!<@brief PORT pin number */
+#define BOARD_INITSPO2PINS_DIAG_END_PIN_MASK (1U << 24U) /*!<@brief PORT pin mask */
+ /* @} */
+
+/*! @name PIO0_27 (number 27), P18[13]/P24[4]/FC2_USART_TXD_ARD
+ @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITSPO2PINS_PD_ALM_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITSPO2PINS_PD_ALM_GPIO_PIN_MASK (1U << 27U) /*!<@brief GPIO pin mask */
+#define BOARD_INITSPO2PINS_PD_ALM_PORT 0U /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITSPO2PINS_PD_ALM_PIN 27U /*!<@brief PORT pin number */
+#define BOARD_INITSPO2PINS_PD_ALM_PIN_MASK (1U << 27U) /*!<@brief PORT pin mask */
+ /* @} */
+
+/*! @name PIO0_16 (number 14), P19[2]/P23[1]/ADC0_N
+ @{ */
+
+/* Symbols to be used with GPIO driver */
+#define BOARD_INITSPO2PINS_LED_ALM_GPIO GPIO /*!<@brief GPIO peripheral base pointer */
+#define BOARD_INITSPO2PINS_LED_ALM_GPIO_PIN_MASK (1U << 16U) /*!<@brief GPIO pin mask */
+#define BOARD_INITSPO2PINS_LED_ALM_PORT 0U /*!<@brief PORT peripheral base pointer */
+#define BOARD_INITSPO2PINS_LED_ALM_PIN 16U /*!<@brief PORT pin number */
+#define BOARD_INITSPO2PINS_LED_ALM_PIN_MASK (1U << 16U) /*!<@brief PORT pin mask */
+ /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitSPO2Pins(void); /* Function assigned for the Cortex-M33 (Core #0) */
+
#if defined(__cplusplus)
}
#endif
diff --git a/include/afe_impl.h b/include/afe_impl.h
new file mode 100644
index 0000000..379f89d
--- /dev/null
+++ b/include/afe_impl.h
@@ -0,0 +1,9 @@
+#ifndef AFE_IMPL_H
+#define AFE_IMPL_H
+
+#include "afe44x0.h"
+
+afe44x0_ret_t afe_impl_init(void);
+afe44x0_ret_t afe_impl_transfer(void *handle, uint8_t *tx_data, uint8_t *rx_data, uint16_t len);
+
+#endif // AFE_IMPL_H
diff --git a/lib/afe44x0/CMakeLists.txt b/lib/afe44x0/CMakeLists.txt
new file mode 100644
index 0000000..f82cd2a
--- /dev/null
+++ b/lib/afe44x0/CMakeLists.txt
@@ -0,0 +1,14 @@
+cmake_minimum_required(VERSION 3.10)
+
+project(afe44x0)
+
+set(AFE44_SOURCES
+ "src/afe44x0.c"
+)
+
+set(AFE44_INCLUDES
+ "include"
+)
+
+add_library(${PROJECT_NAME} ${AFE44_SOURCES})
+target_include_directories(${PROJECT_NAME} PUBLIC ${AFE44_INCLUDES})
\ No newline at end of file
diff --git a/lib/afe44x0/include/afe44x0.h b/lib/afe44x0/include/afe44x0.h
new file mode 100644
index 0000000..e1e5f75
--- /dev/null
+++ b/lib/afe44x0/include/afe44x0.h
@@ -0,0 +1,69 @@
+#ifndef AFE44X0_H
+#define AFE44X0_H
+
+#include
+
+typedef enum {
+ AFE44_RET_SUCCESS,
+ AFE44_RET_FAIL,
+} afe44x0_ret_t;
+
+typedef enum {
+ AFE44_LED_MODE_H_BRIDGE,
+ AFE44_LED_MODE_COMMON_ANODE,
+} afe44x0_led_driver_mode;
+
+typedef enum {
+ AFE44_TIMING_LED2STC = 0x01U, /* Sample LED2 start */
+ AFE44_TIMING_LED2ENDC = 0x02U, /* Sample LED2 end */
+ AFE44_TIMING_LED2LEDSTC = 0x03U, /* Drive LED2 start */
+ AFE44_TIMING_LED2LEDENDC = 0x04U, /* Drive LED2 end */
+ AFE44_TIMING_ALED2STC = 0x05U, /* Sample LED2 ambient start */
+ AFE44_TIMING_ALED2ENDC = 0x06U, /* Sample LED2 ambient end */
+ AFE44_TIMING_LED1STC = 0x07U, /* Sample LED1 start */
+ AFE44_TIMING_LED1ENDC = 0x08U, /* Sample LED1 end */
+ AFE44_TIMING_LED1LEDSTC = 0x09U, /* Drive LED1 start */
+ AFE44_TIMING_LED1LEDENDC = 0x0AU, /* Drive LED1 end */
+ AFE44_TIMING_ALED1STC = 0x0BU, /* Sample LED1 ambient start */
+ AFE44_TIMING_ALED1ENDC = 0x0CU, /* Sample LED1 ambient end */
+ AFE44_TIMING_LED2CONVST = 0x0DU, /* Convert LED2 start */
+ AFE44_TIMING_LED2CONVEND = 0x0EU, /* Convert LED2 end */
+ AFE44_TIMING_ALED2CONVST = 0x0FU, /* Convert LED2 ambient start */
+ AFE44_TIMING_ALED2CONVEND = 0x10U, /* Convert LED2 ambient end */
+ AFE44_TIMING_LED1CONVST = 0x11U, /* Convert LED1 start */
+ AFE44_TIMING_LED1CONVEND = 0x12U, /* Convert LED1 end */
+ AFE44_TIMING_ALED1CONVST = 0x13U, /* Convert LED1 ambient start */
+ AFE44_TIMING_ALED1CONVEND = 0x14U, /* Convert LED1 ambient end */
+ AFE44_TIMING_ADCRSTSTCT0 = 0x15U, /* ADC reset 0 start */
+ AFE44_TIMING_ADCRSTENDCT0 = 0x16U, /* ADC reset 0 end */
+ AFE44_TIMING_ADCRSTSTCT1 = 0x17U, /* ADC reset 1 start */
+ AFE44_TIMING_ADCRSTENDCT1 = 0x18U, /* ADC reset 1 end */
+ AFE44_TIMING_ADCRSTSTCT2 = 0x19U, /* ADC reset 2 start */
+ AFE44_TIMING_ADCRSTENDCT2 = 0x1AU, /* ADC reset 2 end */
+ AFE44_TIMING_ADCRSTSTCT3 = 0x1BU, /* ADC reset 3 start */
+ AFE44_TIMING_ADCRSTENDCT3 = 0x1CU, /* ADC reset 3 end */
+ AFE44_TIMING_PRPCOUNT = 0x1DU, /* PRP count */
+} afe44x0_timing_param_t;
+
+typedef afe44x0_ret_t (*afe44x0_ops_transfer_t)(void *handle, uint8_t *tx_data, uint8_t *rx_data, uint16_t len);
+typedef afe44x0_ret_t (*afe44x0_ops_reset_t)(void *handle);
+
+typedef struct {
+ afe44x0_ops_transfer_t transfer;
+ afe44x0_ops_reset_t reset;
+} afe44x0_ops_t;
+
+typedef struct {
+ afe44x0_timing_param_t param;
+ uint16_t value;
+} afe44x0_timing_t;
+
+typedef struct {
+ afe44x0_ops_t ops;
+ void *user_data;
+} afe44x0_t;
+
+afe44x0_ret_t afe44x0_init(afe44x0_t *afe);
+afe44x0_ret_t afe44x0_apply_timings(afe44x0_t *afe, const afe44x0_timing_t *timings, uint8_t num_timings);
+
+#endif // AFE44X0_H
diff --git a/lib/afe44x0/src/afe44x0.c b/lib/afe44x0/src/afe44x0.c
new file mode 100644
index 0000000..1f122ed
--- /dev/null
+++ b/lib/afe44x0/src/afe44x0.c
@@ -0,0 +1,105 @@
+#include
+
+/* Private */
+#include "afe44x0.h"
+
+#define AFE_ARRAY_SIZE(x) (sizeof(x) / (sizeof(x[0])))
+
+static const afe44x0_timing_t afe44x0_default_timings[] = {
+ {.param = AFE44_TIMING_LED2STC, .value = 6050}, {.param = AFE44_TIMING_LED2ENDC, .value = 7998},
+ {.param = AFE44_TIMING_LED2LEDSTC, .value = 6000}, {.param = AFE44_TIMING_LED2LEDENDC, .value = 7999},
+ {.param = AFE44_TIMING_ALED2STC, .value = 50}, {.param = AFE44_TIMING_ALED2ENDC, .value = 1998},
+ {.param = AFE44_TIMING_LED1STC, .value = 2050}, {.param = AFE44_TIMING_LED1ENDC, .value = 3998},
+ {.param = AFE44_TIMING_LED1LEDSTC, .value = 2000}, {.param = AFE44_TIMING_LED1LEDENDC, .value = 3999},
+ {.param = AFE44_TIMING_ALED1STC, .value = 4050}, {.param = AFE44_TIMING_ALED1ENDC, .value = 5998},
+ {.param = AFE44_TIMING_LED2CONVST, .value = 4}, {.param = AFE44_TIMING_LED2CONVEND, .value = 1999},
+ {.param = AFE44_TIMING_ALED2CONVST, .value = 2004}, {.param = AFE44_TIMING_ALED2CONVEND, .value = 3999},
+ {.param = AFE44_TIMING_LED1CONVST, .value = 4004}, {.param = AFE44_TIMING_LED1CONVEND, .value = 5999},
+ {.param = AFE44_TIMING_ALED1CONVST, .value = 6004}, {.param = AFE44_TIMING_ALED1CONVEND, .value = 7999},
+ {.param = AFE44_TIMING_ADCRSTSTCT0, .value = 0}, {.param = AFE44_TIMING_ADCRSTENDCT0, .value = 3},
+ {.param = AFE44_TIMING_ADCRSTSTCT1, .value = 2000}, {.param = AFE44_TIMING_ADCRSTENDCT1, .value = 2003},
+ {.param = AFE44_TIMING_ADCRSTSTCT2, .value = 4000}, {.param = AFE44_TIMING_ADCRSTENDCT2, .value = 4003},
+ {.param = AFE44_TIMING_ADCRSTSTCT3, .value = 6000}, {.param = AFE44_TIMING_ADCRSTENDCT3, .value = 6003},
+ {.param = AFE44_TIMING_PRPCOUNT, .value = 7999},
+};
+
+static afe44x0_ret_t afe44x0_read_register(afe44x0_t *afe, uint8_t addr, uint32_t *data);
+static afe44x0_ret_t afe44x0_write_register(afe44x0_t *afe, uint8_t addr, uint32_t data);
+static inline afe44x0_ret_t afe44x0_reset(afe44x0_t *afe);
+
+afe44x0_ret_t afe44x0_init(afe44x0_t *afe) {
+ afe44x0_ret_t ret = AFE44_RET_SUCCESS;
+
+ ret = afe44x0_reset(afe);
+ if (ret != AFE44_RET_SUCCESS) {
+ return ret;
+ }
+
+ ret = afe44x0_apply_timings(afe, afe44x0_default_timings, AFE_ARRAY_SIZE(afe44x0_default_timings));
+ return ret;
+}
+
+afe44x0_ret_t afe44x0_apply_timings(afe44x0_t *afe, const afe44x0_timing_t *timings, uint8_t num_timings) {
+ afe44x0_ret_t ret = AFE44_RET_SUCCESS;
+
+ for (uint8_t i = 0; i < num_timings; i++) {
+ ret = afe44x0_write_register(afe->user_data, timings[i].param, timings[i].value);
+ if (ret != AFE44_RET_SUCCESS) {
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static afe44x0_ret_t afe44x0_read_register(afe44x0_t *afe, uint8_t addr, uint32_t *data) {
+ afe44x0_ret_t ret = AFE44_RET_SUCCESS;
+
+ /* Write to Control 0, with SPI_READ bit set */
+ uint8_t tx_buf[4] = {0x00, 0x00, 0x00, 0x01};
+ uint8_t rx_buf[4];
+
+ ret = afe->ops.transfer(afe->user_data, tx_buf, rx_buf, 4);
+ if (ret != AFE44_RET_SUCCESS) {
+ return ret;
+ }
+
+ /* 2nd ops, with address set to register. */
+ tx_buf[0] = addr;
+
+ ret = afe->ops.transfer(afe->user_data, tx_buf, rx_buf, 4);
+ if (ret != AFE44_RET_SUCCESS) {
+ return ret;
+ }
+
+ /* Combine the register contents */
+ *data = rx_buf[1] << 16 | rx_buf[2] << 8 | rx_buf[3];
+
+ return ret;
+}
+
+static afe44x0_ret_t afe44x0_write_register(afe44x0_t *afe, uint8_t addr, uint32_t data) {
+ afe44x0_ret_t ret = AFE44_RET_SUCCESS;
+
+ /* Write to Control 0, with SPI_READ bit set */
+ uint8_t tx_buf[4] = {0x00, 0x00, 0x00, 0x00};
+ uint8_t rx_buf[4];
+
+ ret = afe->ops.transfer(afe->user_data, tx_buf, rx_buf, 4);
+ if (ret != AFE44_RET_SUCCESS) {
+ return ret;
+ }
+
+ tx_buf[0] = addr;
+ tx_buf[1] = (data >> 16U) & 0xFFU;
+ tx_buf[2] = (data >> 8U) & 0xFFU;
+ tx_buf[3] = data & 0xFFU;
+
+ ret = afe->ops.transfer(afe->user_data, tx_buf, rx_buf, 4);
+
+ return ret;
+}
+
+static inline afe44x0_ret_t afe44x0_reset(afe44x0_t *afe) {
+ return afe->ops.reset(afe->user_data);
+}
\ No newline at end of file
diff --git a/src/afe_impl.c b/src/afe_impl.c
new file mode 100644
index 0000000..a05d856
--- /dev/null
+++ b/src/afe_impl.c
@@ -0,0 +1,55 @@
+/* Board */
+#include "pin_mux.h"
+
+/* SDK drivers */
+#include "fsl_spi.h"
+
+/* Private */
+#include "afe_impl.h"
+
+#define AFE_SPI_BASE SPI8
+#define AFE_SPI_CS kSPI_Ssel1
+#define AFE_SPI_ID 8
+#define AFE_SPI_FREQ 4000000UL
+
+afe44x0_ret_t afe_impl_init(void) {
+ spi_master_config_t afe_spi_config = {
+ .enableMaster = true,
+ .polarity = kSPI_ClockPolarityActiveHigh,
+ .phase = kSPI_ClockPhaseFirstEdge,
+ .direction = kSPI_MsbFirst,
+ .baudRate_Bps = AFE_SPI_FREQ,
+ .dataWidth = kSPI_Data8Bits,
+ .sselNum = AFE_SPI_CS,
+ .sselPol = kSPI_SpolActiveAllLow,
+ .txWatermark = kSPI_TxFifo0,
+ .rxWatermark = kSPI_RxFifo1,
+ .delayConfig =
+ {
+ .frameDelay = 0U,
+ .preDelay = 0U,
+ .transferDelay = 0U,
+ .postDelay = 0U,
+ },
+ };
+
+ if (SPI_MasterInit(AFE_SPI_BASE, &afe_spi_config, CLOCK_GetFlexCommClkFreq(AFE_SPI_ID)) != kStatus_Success) {
+ return AFE44_RET_FAIL;
+ }
+
+ return AFE44_RET_SUCCESS;
+}
+
+afe44x0_ret_t afe_impl_transfer(void *handle, uint8_t *tx_data, uint8_t *rx_data, uint16_t len) {
+ spi_transfer_t xfer = {
+ .txData = tx_data,
+ .rxData = rx_data,
+ .dataSize = len,
+ };
+
+ if (SPI_MasterTransferBlocking(AFE_SPI_BASE, &xfer) != kStatus_Success) {
+ return AFE44_RET_FAIL;
+ }
+
+ return AFE44_RET_SUCCESS;
+}
\ No newline at end of file
diff --git a/src/main.c b/src/main.c
index 21245ea..ef34afd 100644
--- a/src/main.c
+++ b/src/main.c
@@ -3,8 +3,21 @@
#include "peripherals.h"
#include "pin_mux.h"
+/* Debug Console */
#include "fsl_debug_console.h"
+/* AFE */
+#include "afe44x0.h"
+#include "afe_impl.h"
+
+static afe44x0_t s_afe = {
+ .ops =
+ {
+ .transfer = afe_impl_transfer,
+ },
+ .user_data = NULL,
+};
+
int main(void) {
BOARD_InitBootPins();
BOARD_BootClockFROHF96M();
@@ -14,7 +27,18 @@ int main(void) {
PRINTF("Hello world!!\r\n");
- for(;;) {
+ if (afe_impl_init() != AFE44_RET_SUCCESS) {
+ PRINTF("Failed to initialize AFE IMPL.\r\n");
+ goto dead_loop;
+ }
+
+ if (afe44x0_init(&s_afe) != AFE44_RET_SUCCESS) {
+ PRINTF("Failed to initialize AFE.\r\n");
+ goto dead_loop;
+ }
+
+dead_loop:
+ for (;;) {
__WFI();
}
}
\ No newline at end of file