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# FDMA
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2022-08-13 15:01:08 +00:00
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The STi7105 SoC has 2 FDMA instances, each FDMA instance has a small CPU called SLIM.
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According to the specs, each FDMA supports 16 concurrent transfers.
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2022-08-11 16:27:33 +00:00
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The firmware of the SLIM processor is required to be loaded into the IMEM and DMEM mapped in
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the FDMA address space. The firmware files can be acquired from STLinux distribution.
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## The CPU
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The `SLIM` CPU is also noted as `STxP70`, which is a 32-bit RISC processor used in some STMicroelectronic products.
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2022-08-13 15:01:08 +00:00
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> Apart from this FDMA, it is also found in VL53L5Cx ToF ranging sensors[[1](#References)].
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2022-08-11 16:27:33 +00:00
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### Firmware
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The firmware is an ELF file which has an `e_machine` of `EM_MAX(102)`, this is reserved
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during the time this processor is developed.
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2022-08-11 16:27:33 +00:00
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2022-08-13 15:01:08 +00:00
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<details>
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<summary>ELF headers of the firmware</summary>
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<pre>
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ELF Header:
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Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
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Class: ELF32
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Data: 2's complement, little endian
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Version: 1 (current)
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OS/ABI: UNIX - System V
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ABI Version: 0
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Type: EXEC (Executable file)
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Machine: MAX Processor
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Version: 0x1
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Entry point address: 0x0
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Start of program headers: 52 (bytes into file)
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Start of section headers: 116 (bytes into file)
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Flags: 0x2
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Size of this header: 52 (bytes)
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Size of program headers: 32 (bytes)
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Number of program headers: 2
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Size of section headers: 40 (bytes)
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Number of section headers: 4
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Section header string table index: 1
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Section Headers:
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[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
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[ 0] NULL 00000000 000000 000000 00 0 0 0
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[ 1] .shstrtab STRTAB 00000000 000114 000017 00 0 0 0
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[ 2] .data PROGBITS fe228000 0036c0 002000 00 A 0 0 32
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[ 3] .text PROGBITS fe22c000 000180 00353c 00 AX 0 0 32
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Key to Flags:
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W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
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L (link order), O (extra OS processing required), G (group), T (TLS),
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C (compressed), x (unknown), o (OS specific), E (exclude),
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D (mbind), p (processor specific)
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There are no section groups in this file.
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Program Headers:
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Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
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LOAD 0x000180 0xfe22c000 0xfe22c000 0x0353c 0x0353c R E 0x20
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LOAD 0x0036c0 0xfe228000 0xfe228000 0x02000 0x02000 R 0x20
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Section to Segment mapping:
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Segment Sections...
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00 .text
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01 .data
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There is no dynamic section in this file.
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There are no relocations in this file.
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The decoding of unwind sections for machine type MAX Processor is not currently supported.
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No version information found in this file.
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</pre>
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</details>
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## Memories
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The SLIM CPU has its dedicated instruction memory(IMEM) and data memory(DMEM).
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### Instruction Memory(IMEM)
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The instruction memory mapped in the FDMA space is unique, the upper 8 bits of each 32bit word is
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always zero. Values written to the MSB will read out as 0, resulting the actual IMEM size is 12kB.
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### Data Memory(DMEM)
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The 8kB data memory is mapped at 0x8000, which can be accessed by both SLIM and the SH4-300 core.
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The data memory also serves as "firmware registers" to the FDMA channel descriptors.
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## Address spaces
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The address space of the FDMA can be categorized as follows:
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SLIM control registers
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| Offset | Size | Name | Remarks |
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|--|--|--|--|
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| 0x0000 | 4 | ID | The ID of the SLIM processor, 0 for STi7105 |
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| 0x0004 | 4 | VER | The version of the SLIM processor, 0 for STi7105 |
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| 0x0008 | 4 | EN | Enable control of the SLIM processor |
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| 0x000C | 4 | CLK_GATE | Clock gate of the SLIM processor |
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Memories
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| Offset | Size | Name | Remarks |
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|--|--|--|--|
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| 0x8000 | 0x2000 | DMEM | Data memory and firmware registers |
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| 0xC000 | 0x4000 | IMEM | Instruction memory, see above. |
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Peripheral control regisers/Mailboxes
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| Offset | Size | Name | Remarks |
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|--|--|--|--|
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| 0xBF88 | 4 | SYNC | STBus sync register |
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| 0xBFC0 | 4 | CMD_STA | Command mailbox |
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| 0xBFC4 | 4 | CMD_SET | See above, set bits |
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| 0xBFC8 | 4 | CMD_CLR | See above, clear bits |
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| 0xBFCC | 4 | CMD_MASK | See above, mask bits |
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| 0xBFD0 | 4 | INT_STA | Interrupt mailbox |
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| 0xBFD4 | 4 | INT_SET | See above, set bits |
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| 0xBFD8 | 4 | INT_CLR | See above, clear bits |
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| 0xBFDC | 4 | INT_MASK | See above, mask bits |
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Firmware registers (shared memory)
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> Address relative to DMEM(BASE + 0x8000)
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| Offset | Size | Name | Remarks |
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|--|--|--|--|
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| 0x0000 | 4 | REVID | firmware revision, major: bit [23:16], minor: bit[15:8]. E.g. 0x00020300 v2.3 |
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| 0x1140 + 4 * n | 4 | CMD_STAT[n] ||
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| 0x1180 + 4 * n | 4 | REQ_CTL[n] ||
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| 0x1580 + 64 * n | 64 | CHANNEL_DESC[n] | Channel descriptors, see below |
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Channel descriptor
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| Offset | Size | Name | Remarks |
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|--|--|--|--|
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| 0x0000 | 4 | PTR ||
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| 0x0008 | 4 | CNT ||
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| 0x000C | 4 | SADDR ||
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| 0x0010 | 4 | DADDR ||
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## References
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\[1\]: https://the6p4c.github.io/2022/06/13/stxp70-sthorm-p2012.html
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