diff --git a/Boot.md b/Boot.md
index 6ee40d2..336b8dc 100644
--- a/Boot.md
+++ b/Boot.md
@@ -1,19 +1,9 @@
 # STi7105 hardware boot procedure
 
 ## What we have learned
-* STi7105 starts execution at address `0x0000_0000`, in little endian mode.
-* Boot from SPI flash: the flash is mapped to EMI address space at `0x0000_0000`, determined by hardware pins.
-* The initialization process configures a bunch of registers, incl. clock and peripherals.
-* SH-4 CPU has two address modes, either 29bits or 32bits. The memory mapping for both modes is different.
-* As on-chip RAM is never found in documentation, we can assume that LMI DDR2 SDRAM is initialized before execution starts
-* ...which probably initialized by hardware or BootROM.
-* The LMI is mapped at `0x0C00_0000` in 29bit mode, `0x4000_0000` in 32bit mode.
-* The Github repo contains board support for this specific board(GB620)
-* Red LED is `P0_4`, Green LED is `P0_5`
-
-## TODO
-* Proper lds for bare metal testing
-* Proper assembly startup for bare metal testing
-
-## Supplementary files
-[Check Here](https://cloud.imi.moe/s/AFzsnEKNfxQYjjC)
+* STi7105 starts execution at address `0xA000_0000`, in little endian mode.
+* Boot from SPI flash: the flash is mapped to EMI address space at `0xA000_0000`, determined by hardware pins.
+* In 29-bit mode, these ranges are the same EMI address space as the processor simply discarded the higher 3 address bits.
+* The EMI can only be accessed in 32 bits, so XIP cannot be achieved.
+* MMU is forced active in 32bit(SE) mode, TLB or PMB has to be configured before mode switching
+* Most address space which PMB can configure is in P2/P3, which cannot be accessed when in user mode (U0)
diff --git a/README.md b/README.md
index 3469c8e..afc6cab 100644
--- a/README.md
+++ b/README.md
@@ -9,4 +9,13 @@
 | Red LED | PIO0_4 | N/A (GPIO) | Active low |
 | Blue LED | PIO0_5 | N/A (GPIO) | Active low |
 | UART header TX | PIO4_0 | ALT_3 | ASC2 |
-| UART header RX | PIO4_1 | ALT_3 | ASC2, Default routed |
\ No newline at end of file
+| UART header RX | PIO4_1 | ALT_3 | ASC2, Default routed |
+
+## TODO
+* FreeRTOS
+* More peripheral drivers
+* U-Boot (finally)
+* Linux Kernel (in some future we can't expect)
+
+## Supplementary files
+[Check Here](https://cloud.imi.moe/s/AFzsnEKNfxQYjjC)
\ No newline at end of file