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ibex_demo
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Removed ddr dump.

This commit is contained in:
imi415 2020-06-01 18:05:19 +08:00
parent 38deee9f94
commit a5c589c0a2
Signed by: imi415
GPG Key ID: 17F01E106F9F5E0A
3 changed files with 11 additions and 22 deletions
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4
linker.ld
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@ -8,8 +8,8 @@ _minimum_heap_size = 0x2000;
MEMORY
{
RO_CODE (rx) : ORIGIN = 0x42000000, LENGTH = 128K
RW_DATA (xrw) : ORIGIN = 0x42020000, LENGTH = 128K
RO_CODE (rx) : ORIGIN = 0x42000000, LENGTH = 192K
RW_DATA (xrw) : ORIGIN = 0x42030000, LENGTH = 64K
}
SECTIONS

16
src/main.c
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@ -11,24 +11,14 @@ xilinx_uartlite_handle_t soc_uart;
xilinx_gpio_handle_t soc_gpio;
int main(int argc, char *argv[]) {
printf("Dumping first 256 bytes of DDR memory...\r\n");
for(uint32_t i = DDR_BASE; i < DDR_BASE + DDR_LENGTH; i++) {
printf("%02x ", *(uint8_t *)i);
if((i + 1) % 16 == 0) {
printf("\r\n");
}
}
printf("Dump done.\r\n");
printf("== RISC-V: The Free and Open RISC Instruction Set Architecture ==\r\n");
printf("Running on LowRISC Ibex\r\n");
printf("System core frequency: %ld\r\n", GetCoreClock());
volatile uint32_t reg_buf = 0;
asm volatile("csrr %0, misa\n" : "=r"(reg_buf));
__csrr("misa", reg_buf);
printf("MISA: 0x%08x\r\n", reg_buf);
asm volatile("csrr %0, mhartid\n" : "=r"(reg_buf));
__csrr("mhartid", reg_buf);
printf("MHARTID: 0x%08x\r\n", reg_buf);
uint32_t previous_tick = GetTick();
@ -41,7 +31,7 @@ int main(int argc, char *argv[]) {
previous_tick = GetTick();
xilinx_gpio_toggle(&soc_gpio, 1);
printf("SysTick: %lu\r\n", GetTick());
printf("MCycle: %llu\r\n", __read_mcycle());
printf("MCycle: %016llx\r\n", __read_mcycle());
}
}
return 0;

13
src/system_init.c
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@ -1,5 +1,3 @@
#include "xilinx_timer.h"
#include "main.h"
__IO uint32_t SysTick;
@ -14,15 +12,16 @@ void System_Init(void) {
SysTick = 0;
// Enable interrupts
__enable_irqn(TIMER_IRQn); // Enable timer interrupt
__enable_irqs();
__enable_mcount();
// Setup systick timer
TIMER0->TCSR0 = 0x12; // Generate mode, down count, auto-reload
TIMER0->TCR0 = 0; // Clear counter
TIMER0->TCSR0 = 0x112; // Generate mode, down count, auto-reload
TIMER0->TLR0 = SYS_CLK_FREQ / SYS_TICK_RATE; // Set reload value
TIMER0->TCSR0 |= (1U << 0x05);
TIMER0->TCSR0 &= ~(1U << 0x05);
TIMER0->TCSR0 |= (1 << 0x06U) | (1 << 0x07U); // Enable timer interrupt, enable counter.
__enable_irqn(TIMER_IRQn); // Enable timer interrupt
TIMER0->TCSR0 |= (1U << 0x06) | (1U << 0x07); // Enable timer interrupt, enable counter.
}