#include #include #include "main.h" #define DDR_BASE 0x1FC00000 #define DDR_LENGTH 0x100 xilinx_uartlite_handle_t soc_uart; xilinx_gpio_handle_t soc_gpio; int main(int argc, char *argv[]) { printf("Dumping first 256 bytes of DDR memory...\r\n"); for(uint32_t i = DDR_BASE; i < DDR_BASE + DDR_LENGTH; i++) { printf("%02x ", *(uint8_t *)i); if((i + 1) % 16 == 0) { printf("\r\n"); } } printf("Dump done.\r\n"); printf("== RISC-V: The Free and Open RISC Instruction Set Architecture ==\r\n"); printf("Running on LowRISC Ibex\r\n"); printf("System core frequency: %ld\r\n", GetCoreClock()); volatile uint32_t reg_buf = 0; asm volatile("csrr %0, misa\n" : "=r"(reg_buf)); printf("MISA: 0x%08x\r\n", reg_buf); asm volatile("csrr %0, mhartid\n" : "=r"(reg_buf)); printf("MHARTID: 0x%08x\r\n", reg_buf); uint32_t previous_tick = GetTick(); xilinx_gpio_pinmode(&soc_gpio, 1, 1); xilinx_gpio_write(&soc_gpio, 1, 0); while(1) { if(GetTick() - previous_tick >= 500) { previous_tick = GetTick(); xilinx_gpio_toggle(&soc_gpio, 1); printf("SysTick: %lu\r\n", GetTick()); printf("MCycle: %llu\r\n", __read_mcycle()); } } return 0; }