From e44c9f6664c57e8d3f060e70989c685660a933ef Mon Sep 17 00:00:00 2001 From: imi415 Date: Tue, 15 Sep 2020 00:25:45 +0800 Subject: [PATCH] Multiple fixes. * Removed obsolete openocd config, use -c 'set WORKAREASIZE 0' on devices except ST-LINK and CMSIS-DAP debugger. * Removed logger functions due to non-reentrant logger API. --- config/FreeRTOSConfig.h | 4 +-- config/sdk_config.h | 10 +++---- main.c | 9 ++++-- nrf51.cfg | 61 ----------------------------------------- 4 files changed, 13 insertions(+), 71 deletions(-) delete mode 100644 nrf51.cfg diff --git a/config/FreeRTOSConfig.h b/config/FreeRTOSConfig.h index 3b5b885..b9203b7 100644 --- a/config/FreeRTOSConfig.h +++ b/config/FreeRTOSConfig.h @@ -91,9 +91,9 @@ #define configTICK_SOURCE FREERTOS_USE_RTC -#define configUSE_PREEMPTION 1 +#define configUSE_PREEMPTION 1 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#define configUSE_TICKLESS_IDLE 1 +#define configUSE_TICKLESS_IDLE 1 #define configUSE_TICKLESS_IDLE_SIMPLE_DEBUG 1 /* See into vPortSuppressTicksAndSleep source code for explanation */ #define configCPU_CLOCK_HZ ( SystemCoreClock ) #define configTICK_RATE_HZ 1000 diff --git a/config/sdk_config.h b/config/sdk_config.h index 757cb24..12bc134 100644 --- a/config/sdk_config.h +++ b/config/sdk_config.h @@ -261,7 +261,7 @@ // UART_CONFIG_LOG_ENABLED - Enables logging in the module. //========================================================== #ifndef UART_CONFIG_LOG_ENABLED -#define UART_CONFIG_LOG_ENABLED 1 +#define UART_CONFIG_LOG_ENABLED 0 #endif #if UART_CONFIG_LOG_ENABLED // UART_CONFIG_LOG_LEVEL - Default Severity level @@ -273,7 +273,7 @@ // <4=> Debug #ifndef UART_CONFIG_LOG_LEVEL -#define UART_CONFIG_LOG_LEVEL 4 +#define UART_CONFIG_LOG_LEVEL 3 #endif // UART_CONFIG_INFO_COLOR - ANSI escape code prefix. @@ -289,7 +289,7 @@ // <8=> White #ifndef UART_CONFIG_INFO_COLOR -#define UART_CONFIG_INFO_COLOR 3 +#define UART_CONFIG_INFO_COLOR 0 #endif // UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. @@ -305,7 +305,7 @@ // <8=> White #ifndef UART_CONFIG_DEBUG_COLOR -#define UART_CONFIG_DEBUG_COLOR 6 +#define UART_CONFIG_DEBUG_COLOR 0 #endif #endif //UART_CONFIG_LOG_ENABLED @@ -505,7 +505,7 @@ // <268435456=> 57600 baud #ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE -#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30924800 +#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 251658240 #endif // NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin diff --git a/main.c b/main.c index 6a8bdd2..5aef0ca 100644 --- a/main.c +++ b/main.c @@ -8,10 +8,13 @@ #include "nordic_common.h" #include "sdk_errors.h" #include "app_error.h" +#include "nrf_log.h" +#include "nrf_log_ctrl.h" #include "FreeRTOS.h" #include "task.h" #include "timers.h" +#include "semphr.h" #define APP_TIMER_PRESCALER 0 #define APP_TIMER_OP_QUEUE_SIZE 4 @@ -20,7 +23,7 @@ TaskHandle_t xTaskBlinkLEDHandle = NULL; void vTaskBlinkLED(void *pvParameters); TimerHandle_t xTimerBlinkAnotherLEDHandle = NULL; -void xTimerBlinkAnotherLEDCallback(void *pvParameters); +void xTimerBlinkAnotherLEDCallback(TimerHandle_t xTimer); int main(void) { ret_code_t err_code; @@ -53,7 +56,7 @@ void vTaskBlinkLED(void *pvParameters) { } } -void xTimerBlinkAnotherLEDCallback(void *pvParameters) { - UNUSED_VARIABLE(pvParameters); +void xTimerBlinkAnotherLEDCallback(TimerHandle_t xTimer) { + UNUSED_VARIABLE(xTimer); bsp_board_led_invert(BSP_BOARD_LED_1); } \ No newline at end of file diff --git a/nrf51.cfg b/nrf51.cfg deleted file mode 100644 index 6cb92c6..0000000 --- a/nrf51.cfg +++ /dev/null @@ -1,61 +0,0 @@ -# -# script for Nordic nRF51 series, a Cortex-M0 chip -# - -source [find target/swj-dp.tcl] - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME nrf51 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 16kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0 -} - -if { [info exists CPUTAPID] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x0bb11477 -} - -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -if {![using_hla]} { - # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal - cortex_m reset_config sysresetreq -} - -flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME -flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME - -# -# The chip should start up from internal 16Mhz RC, so setting adapter -# clock to 1Mhz should be OK -# -adapter speed 1000 - -proc enable_all_ram {} { - # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks - # are reliably enabled after reset on some revisions (contrary to spec.) So after - # resetting we enable all banks via the RAMON register - mww 0x40000524 0xF -} -$_TARGETNAME configure -event reset-end { enable_all_ram }