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openocd/src/rtos/rtos_standard_stackings.h

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openocd: src/rtos: replace the GPL-2.0-or-later license tag Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: If0194089baded7f58dc5d87a35d6e0aff9f43785 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7070 Tested-by: jenkins
2022-06-26 23:10:12 +00:00
/* SPDX-License-Identifier: GPL-2.0-or-later */
RTOS Thread awareness support wip - works on Cortex-M3 with ThreadX and FreeRTOS Compared to original patch a few nits were fixed: - remove stricmp usage - unsigned compare fix - printf formatting fixes - fixed a bug with overrunning a memory buffer allocated with malloc.
2011-04-14 08:25:01 +00:00
/***************************************************************************
* Copyright (C) 2011 by Broadcom Corporation *
* Evan Hunter - ehunter@broadcom.com *
***************************************************************************/
Make #include guard naming consistent Change-Id: Ie13e8af0bb74ed290f811dcad64ad06c9d8cb4fa Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2956 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-09-21 19:07:46 +00:00
#ifndef OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H
#define OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H
RTOS Thread awareness support wip - works on Cortex-M3 with ThreadX and FreeRTOS Compared to original patch a few nits were fixed: - remove stricmp usage - unsigned compare fix - printf formatting fixes - fixed a bug with overrunning a memory buffer allocated with malloc.
2011-04-14 08:25:01 +00:00
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "rtos.h"
rtos: rename CamelCase symbols Only one exported symbol from eCos is included in this patch. The eCos code is left untouched to prevent conflicts with patches currently under review. While there, remove an unused camelcase macro Change-Id: I8d22dec6e243c00665d99a8b8ba00474b4f088db Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6305 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de>
2021-05-25 07:55:22 +00:00
extern const struct rtos_register_stacking rtos_standard_cortex_m3_stacking;
extern const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking;
extern const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking;
extern const struct rtos_register_stacking rtos_standard_cortex_r4_stacking;
extern const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking;
uint64_t->target_addr_t for stack pointers. This might be incomplete. It's just a quick attempt to reduce some of the difference between riscv-openocd and mainline. Other stack pointers can be updated as I come across them. Change-Id: Id3311b8a1bb0667f309a26d36b67093bfeb8380a Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6586 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-21 18:43:21 +00:00
target_addr_t rtos_generic_stack_align8(struct target *target,
rtos: turn stack alignment into a function pointer Some targets (Cortex M) require more complicated calculations for turning the stored stack pointer back into a process stack pointer. For example, the Cortex M stores a bit in the auto-stacked xPSR indicating that alignment had to be performed and an additional 4 byte padding is present before the exception stacking. This change only sets up the framework for Cortex-M unstacking and does not add Cortex-M support. Note: this also fixes the alignment calculation nearly addressed by change #2301 entitled rtos/rtos.c: fix stack alignment calculation. Updated calculation is in rtos_generic_stack_align. Change-Id: I0f662cad0df81cbe5866219ad0fef980dcb3e44f Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Paul Fertser <fercerpav@gmail.com> Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com> Cc: Evan Hunter <evanhunter920@gmail.com> Cc: Jon Burgess <jburgess777@gmail.com> Reviewed-on: http://openocd.zylin.com/3002 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2015-10-05 18:51:10 +00:00
const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
uint64_t->target_addr_t for stack pointers. This might be incomplete. It's just a quick attempt to reduce some of the difference between riscv-openocd and mainline. Other stack pointers can be updated as I come across them. Change-Id: Id3311b8a1bb0667f309a26d36b67093bfeb8380a Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6586 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-21 18:43:21 +00:00
target_addr_t stack_ptr);
target_addr_t rtos_cortex_m_stack_align(struct target *target,
rtos: handle STKALIGN adjustments on cortex m In the case that the STKALIGN bit is set on Cortex M processors, on entry to an exception - the processor can store an additional 4 bytes of padding before regular stacking to achieve 8-byte alignment on exception entry. In the case that this padding is present, the processor will set bit (1 << 9) in the stacked xPSR register. Use the new calculate_process_stack callback to take into account the xPSR register and use it on the standard Cortex_M3 stacking. Note: Change #2301 had some misinformation regarding the padding. On Cortex-M the padding is stored BEFORE stacking so xPSR is always available at a fixed offset. Tested on a Cortex-M0+ (Atmel SAMR21) board which has STKALIGN fixed to a '1' such that this alignment always occurs on non-aligned stacks. Behavior of xPSR verified via the (bad-sorry) assembly program below by setting a breakpoint on the SVC_Handler symbol. The first time SVC_Handler is triggered the stack was 0x20000ff8, the second time SVC_Handler is triggered the stack was 0x20000ffc. Note that in both cases the interrupt handler gets 0x20000fd8 for a stack pointer. GDB exerpt: Breakpoint 1, 0x000040b6 in Reset_Handler () (gdb) hbreak SVC_Handler Hardware assisted breakpoint 2 at 0x40f8 (gdb) cont Continuing. Breakpoint 2, 0x000040f8 in SVC_Handler () (gdb) print $msp $3 = (void *) 0x20000fd8 (gdb) x/9w $msp 0x20000fd8: 0x1 0x2 0x3 0x4 0x20000fe8: 0x88160082 0xa53 0x40ce 0x21000000 0x20000ff8: 0x0 (gdb) cont Continuing. Breakpoint 2, 0x000040f8 in SVC_Handler () (gdb) print $msp $4 = (void *) 0x20000fd8 (gdb) x/9w $msp 0x20000fd8: 0x1 0x2 0x3 0x4 0x20000fe8: 0x88160082 0xa53 0x40e8 0x21000200 0x20000ff8: 0x0 Assembly program: .cpu cortex-m0plus .fpu softvfp .thumb .syntax unified .section .vectors @ pvStack: .word 0x20001000 @ pfnReset_Handler: .word Reset_Handler + 1 @ pfnNMI_Handler: .word 0 @ pfnHardFault_Handler: .word 0 @ pfnReservedM12: .word 0 @ pfnReservedM11: .word 0 @ pfnReservedM10: .word 0 @ pfnReservedM9: .word 0 @ pfnReservedM8: .word 0 @ pfnReservedM7: .word 0 @ pfnReservedM6: .word 0 @ pfnSVC_Handler: .word SVC_Handler + 1 .section .text .global Reset_Handler Reset_Handler: cpsie i ldr r0, .stack_start ldr r2, .stack_last eors r1, r1 .loop_clear: str r1, [r0] adds r0, r0, #4 cmp r0, r2 bne .loop_clear subs r2, r2, #4 mov sp, r2 movs r0, #1 movs r1, #2 movs r2, #3 movs r3, #4 svc #0 ldr r0, .stack_start ldr r2, .stack_last eors r1, r1 .loop_clear2: str r1, [r0] adds r0, r0, #4 cmp r0, r2 bne .loop_clear2 mov sp, r2 movs r0, #1 movs r1, #2 movs r2, #3 movs r3, #4 svc #0 .loop: b .loop .align 4 .stack_start: .word 0x20000f00 .stack_last: .word 0x20000ffc @ first call - 0x2000fff8 -- should already be aligned @ second call - 0x2000fffc -- should hit the alignment code .global SVC_Handler SVC_Handler: bx lr Change-Id: Id0940e6bbd6a59adee1378c0e86fe86830f0c8fc Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Paul Fertser <fercerpav@gmail.com> Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com> Cc: Evan Hunter <evanhunter920@gmail.com> Cc: Jon Burgess <jburgess777@gmail.com> Reviewed-on: http://openocd.zylin.com/3003 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-10-05 18:52:43 +00:00
const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
uint64_t->target_addr_t for stack pointers. This might be incomplete. It's just a quick attempt to reduce some of the difference between riscv-openocd and mainline. Other stack pointers can be updated as I come across them. Change-Id: Id3311b8a1bb0667f309a26d36b67093bfeb8380a Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6586 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2021-09-21 18:43:21 +00:00
target_addr_t stack_ptr, size_t xpsr_offset);
RTOS Thread awareness support wip - works on Cortex-M3 with ThreadX and FreeRTOS Compared to original patch a few nits were fixed: - remove stricmp usage - unsigned compare fix - printf formatting fixes - fixed a bug with overrunning a memory buffer allocated with malloc.
2011-04-14 08:25:01 +00:00
Make #include guard naming consistent Change-Id: Ie13e8af0bb74ed290f811dcad64ad06c9d8cb4fa Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/2956 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-09-21 19:07:46 +00:00
#endif /* OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H */