2008-07-26 10:32:11 +00:00
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/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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2011-07-07 15:41:20 +00:00
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* Copyright (C) 2011 by Drasko DRASKOVIC *
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* drasko.draskovic@gmail.com *
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* *
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2008-07-26 10:32:11 +00:00
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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2013-06-02 19:32:36 +00:00
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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2008-07-26 10:32:11 +00:00
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***************************************************************************/
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2012-02-05 12:03:04 +00:00
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2008-07-26 10:32:11 +00:00
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#ifndef MIPS32_PRACC_H
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#define MIPS32_PRACC_H
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2009-12-16 11:23:52 +00:00
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#include <target/mips32.h>
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#include <target/mips_ejtag.h>
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2008-07-26 10:32:11 +00:00
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2009-12-16 11:23:52 +00:00
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#define MIPS32_PRACC_FASTDATA_AREA 0xFF200000
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#define MIPS32_PRACC_FASTDATA_SIZE 16
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2013-12-01 09:40:34 +00:00
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#define MIPS32_PRACC_BASE_ADDR 0xFF200000
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2010-01-07 20:56:07 +00:00
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#define MIPS32_PRACC_TEXT 0xFF200200
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2013-12-01 09:40:34 +00:00
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#define MIPS32_PRACC_PARAM_OUT 0xFF202000
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2008-07-26 10:32:11 +00:00
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2012-11-01 19:55:28 +00:00
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#define PRACC_UPPER_BASE_ADDR (MIPS32_PRACC_BASE_ADDR >> 16)
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#define PRACC_OUT_OFFSET (MIPS32_PRACC_PARAM_OUT - MIPS32_PRACC_BASE_ADDR)
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2009-12-16 11:23:52 +00:00
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#define MIPS32_FASTDATA_HANDLER_SIZE 0x80
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2011-07-07 15:41:20 +00:00
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#define UPPER16(uint32_t) (uint32_t >> 16)
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#define LOWER16(uint32_t) (uint32_t & 0xFFFF)
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#define NEG16(v) (((~(v)) + 1) & 0xFFFF)
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2009-06-23 22:47:42 +00:00
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/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
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2008-07-26 10:32:11 +00:00
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mips: m4k alternate pracc code. Patch 1
This patch and the following patches define another way of doing processor access without the need to read back
the pracc address as needed in current pracc code.
Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
Most of the processor accesses are fetch and some are store accesses.
After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
The pracc address for a store depends only on the store instruction given before.
m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
For reference: MD00249 mips32 m4k manual.
A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
current code or by the new one to generate the sequence of pracc accesses.
For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
The pracc bit is not checked before execution, is checked after the queue has been executed.
Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
between scans is added by calling jtag_add_cloks().
A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
current code is executed, if lower, new code is executed.
Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1193
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-03-03 09:50:42 +00:00
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struct pracc_queue_info {
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int retval;
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const int max_code;
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int code_count;
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int store_count;
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uint32_t *pracc_list; /* Code and store addresses */
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};
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2013-03-03 19:11:38 +00:00
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void pracc_queue_init(struct pracc_queue_info *ctx);
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void pracc_add(struct pracc_queue_info *ctx, uint32_t addr, uint32_t instr);
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void pracc_queue_free(struct pracc_queue_info *ctx);
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int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info,
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struct pracc_queue_info *ctx, uint32_t *buf);
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mips: m4k alternate pracc code. Patch 1
This patch and the following patches define another way of doing processor access without the need to read back
the pracc address as needed in current pracc code.
Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
Most of the processor accesses are fetch and some are store accesses.
After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
The pracc address for a store depends only on the store instruction given before.
m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
For reference: MD00249 mips32 m4k manual.
A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
current code or by the new one to generate the sequence of pracc accesses.
For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
The pracc bit is not checked before execution, is checked after the queue has been executed.
Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
between scans is added by calling jtag_add_cloks().
A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
current code is executed, if lower, new code is executed.
Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1193
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-03-03 09:50:42 +00:00
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2009-11-13 16:43:36 +00:00
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int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info,
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2009-11-09 12:22:23 +00:00
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uint32_t addr, int size, int count, void *buf);
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2009-11-13 16:43:36 +00:00
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int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
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2013-09-30 21:16:20 +00:00
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uint32_t addr, int size, int count, const void *buf);
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2009-12-16 11:23:52 +00:00
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int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
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2010-12-29 20:15:48 +00:00
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int write_t, uint32_t addr, int count, uint32_t *buf);
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2008-07-26 10:32:11 +00:00
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2009-11-13 16:43:36 +00:00
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int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
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2008-07-26 10:32:11 +00:00
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2013-12-03 22:25:20 +00:00
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int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx, uint32_t *param_out);
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2008-07-26 10:32:11 +00:00
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2011-07-07 15:41:20 +00:00
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/**
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* \b mips32_cp0_read
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*
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* Simulates mfc0 ASM instruction (Move From C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Storage to hold read value
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* @param[in] cp0_reg Number of copro C0 register we want to read
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_read(struct mips_ejtag *ejtag_info,
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2012-02-05 12:03:04 +00:00
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uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
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2011-07-07 15:41:20 +00:00
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/**
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* \b mips32_cp0_write
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*
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* Simulates mtc0 ASM instruction (Move To C0),
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* i.e. implements copro C0 Register read.
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*
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* @param[in] ejtag_info
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* @param[in] val Value to be written
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* @param[in] cp0_reg Number of copro C0 register we want to write to
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* @param[in] cp0_sel Select for the given C0 register
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*
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* @return ERROR_OK on Sucess, ERROR_FAIL otherwise
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*/
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int mips32_cp0_write(struct mips_ejtag *ejtag_info,
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2012-02-05 12:03:04 +00:00
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uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
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2011-07-07 15:41:20 +00:00
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2008-07-26 10:32:11 +00:00
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#endif
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