2008-02-25 08:01:21 +00:00
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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2008-07-23 14:49:41 +00:00
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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2008-08-18 17:11:43 +00:00
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*
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* Copyright (C) 2008 by Oyvind Harboe *
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* oyvind.harboe@zylin.com *
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2008-07-23 14:49:41 +00:00
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* *
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2008-02-25 08:01:21 +00:00
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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2009-12-04 22:06:20 +00:00
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#include "imp.h"
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2008-02-25 08:01:21 +00:00
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#include "str9x.h"
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2009-12-03 12:14:38 +00:00
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#include <target/arm966e.h>
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2009-12-03 12:14:35 +00:00
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#include <target/algorithm.h>
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2008-02-25 08:01:21 +00:00
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2009-06-18 07:10:25 +00:00
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static uint32_t bank1start = 0x00080000;
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2008-02-25 08:01:21 +00:00
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2009-11-13 19:32:28 +00:00
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static int str9x_build_block_list(struct flash_bank *bank)
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2008-02-25 08:01:21 +00:00
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{
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2009-11-13 15:39:12 +00:00
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struct str9x_flash_bank *str9x_info = bank->driver_priv;
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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int i;
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2008-04-14 07:26:13 +00:00
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int num_sectors;
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2008-02-25 08:01:21 +00:00
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int b0_sectors = 0, b1_sectors = 0;
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2009-06-18 07:10:25 +00:00
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uint32_t offset = 0;
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2009-06-01 03:05:26 +00:00
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2008-04-14 07:26:13 +00:00
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/* set if we have large flash str9 */
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str9x_info->variant = 0;
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str9x_info->bank1 = 0;
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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switch (bank->size)
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{
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case (256 * 1024):
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b0_sectors = 4;
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break;
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case (512 * 1024):
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b0_sectors = 8;
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break;
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2008-04-14 07:26:13 +00:00
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case (1024 * 1024):
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bank1start = 0x00100000;
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str9x_info->variant = 1;
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b0_sectors = 16;
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break;
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case (2048 * 1024):
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bank1start = 0x00200000;
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str9x_info->variant = 1;
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b0_sectors = 32;
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break;
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case (128 * 1024):
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str9x_info->variant = 1;
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str9x_info->bank1 = 1;
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b1_sectors = 8;
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bank1start = bank->base;
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break;
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2008-02-25 08:01:21 +00:00
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case (32 * 1024):
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2008-04-14 07:26:13 +00:00
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str9x_info->bank1 = 1;
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2008-02-25 08:01:21 +00:00
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b1_sectors = 4;
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bank1start = bank->base;
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break;
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default:
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2008-03-25 15:45:17 +00:00
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LOG_ERROR("BUG: unknown bank->size encountered");
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2008-02-25 08:01:21 +00:00
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exit(-1);
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}
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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num_sectors = b0_sectors + b1_sectors;
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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bank->num_sectors = num_sectors;
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2009-11-13 15:37:54 +00:00
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bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
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2009-06-18 07:10:25 +00:00
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str9x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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num_sectors = 0;
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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for (i = 0; i < b0_sectors; i++)
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{
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2008-04-14 07:26:13 +00:00
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bank->sectors[num_sectors].offset = offset;
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bank->sectors[num_sectors].size = 0x10000;
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offset += bank->sectors[i].size;
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2008-02-25 08:01:21 +00:00
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bank->sectors[num_sectors].is_erased = -1;
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bank->sectors[num_sectors].is_protected = 1;
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2009-06-23 22:41:13 +00:00
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str9x_info->sector_bits[num_sectors++] = (1 << i);
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2008-02-25 08:01:21 +00:00
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}
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for (i = 0; i < b1_sectors; i++)
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{
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2008-04-14 07:26:13 +00:00
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bank->sectors[num_sectors].offset = offset;
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bank->sectors[num_sectors].size = str9x_info->variant == 0 ? 0x2000 : 0x4000;
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offset += bank->sectors[i].size;
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2008-02-25 08:01:21 +00:00
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bank->sectors[num_sectors].is_erased = -1;
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bank->sectors[num_sectors].is_protected = 1;
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2008-04-14 07:26:13 +00:00
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if (str9x_info->variant)
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2009-06-23 22:41:13 +00:00
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str9x_info->sector_bits[num_sectors++] = (1 << i);
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2008-04-14 07:26:13 +00:00
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else
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2009-06-23 22:44:17 +00:00
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str9x_info->sector_bits[num_sectors++] = (1 << (i + 8));
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2008-02-25 08:01:21 +00:00
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}
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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return ERROR_OK;
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}
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/* flash bank str9x <base> <size> 0 0 <target#>
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*/
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2009-11-10 09:41:30 +00:00
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FLASH_BANK_COMMAND_HANDLER(str9x_flash_bank_command)
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2008-02-25 08:01:21 +00:00
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{
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2009-11-13 15:39:12 +00:00
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struct str9x_flash_bank *str9x_info;
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2009-06-01 03:05:26 +00:00
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2009-11-15 12:57:12 +00:00
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if (CMD_ARGC < 6)
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2008-02-25 08:01:21 +00:00
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{
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2008-03-25 15:45:17 +00:00
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LOG_WARNING("incomplete flash_bank str9x configuration");
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2008-02-25 08:01:21 +00:00
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return ERROR_FLASH_BANK_INVALID;
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}
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2009-06-01 03:05:26 +00:00
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2009-11-13 15:39:12 +00:00
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str9x_info = malloc(sizeof(struct str9x_flash_bank));
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2008-02-25 08:01:21 +00:00
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bank->driver_priv = str9x_info;
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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str9x_build_block_list(bank);
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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str9x_info->write_algorithm = NULL;
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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return ERROR_OK;
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}
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2009-11-13 19:32:28 +00:00
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static int str9x_protect_check(struct flash_bank *bank)
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2008-02-25 08:01:21 +00:00
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{
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2008-08-18 17:11:43 +00:00
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int retval;
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2009-11-13 15:39:12 +00:00
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struct str9x_flash_bank *str9x_info = bank->driver_priv;
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2009-11-13 18:11:13 +00:00
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struct target *target = bank->target;
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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int i;
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2009-06-18 07:10:25 +00:00
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uint32_t adr;
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uint32_t status = 0;
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2009-06-18 07:07:59 +00:00
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uint16_t hstatus = 0;
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2008-02-25 08:01:21 +00:00
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if (bank->target->state != TARGET_HALTED)
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{
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2008-08-17 19:40:17 +00:00
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LOG_ERROR("Target not halted");
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2008-02-25 08:01:21 +00:00
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return ERROR_TARGET_NOT_HALTED;
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}
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/* read level one protection */
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2009-06-01 03:05:26 +00:00
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2008-04-14 07:26:13 +00:00
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if (str9x_info->variant)
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{
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if (str9x_info->bank1)
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{
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adr = bank1start + 0x18;
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2009-06-23 22:42:54 +00:00
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if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
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2008-08-18 17:11:43 +00:00
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{
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return retval;
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}
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2009-06-23 22:42:54 +00:00
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if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
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2008-08-18 17:11:43 +00:00
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{
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return retval;
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}
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2009-04-21 05:36:53 +00:00
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status = hstatus;
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2008-04-14 07:26:13 +00:00
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}
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else
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{
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adr = bank1start + 0x14;
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2009-06-23 22:42:54 +00:00
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if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
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2008-08-18 17:11:43 +00:00
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{
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return retval;
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}
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2009-06-23 22:42:54 +00:00
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if ((retval = target_read_u32(target, adr, &status)) != ERROR_OK)
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2008-08-18 17:11:43 +00:00
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{
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return retval;
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}
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2008-04-14 07:26:13 +00:00
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}
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}
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else
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{
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adr = bank1start + 0x10;
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2009-06-23 22:42:54 +00:00
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if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
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2008-08-18 17:11:43 +00:00
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{
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return retval;
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}
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2009-06-23 22:42:54 +00:00
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if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
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2008-08-18 17:11:43 +00:00
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{
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return retval;
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}
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2009-04-21 05:36:53 +00:00
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status = hstatus;
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2008-04-14 07:26:13 +00:00
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}
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2009-06-01 03:05:26 +00:00
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2008-04-26 12:50:03 +00:00
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/* read array command */
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2009-06-23 22:42:54 +00:00
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if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
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2008-08-18 17:11:43 +00:00
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{
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return retval;
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}
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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for (i = 0; i < bank->num_sectors; i++)
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{
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if (status & str9x_info->sector_bits[i])
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bank->sectors[i].is_protected = 1;
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else
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bank->sectors[i].is_protected = 0;
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}
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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return ERROR_OK;
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}
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2009-11-13 19:32:28 +00:00
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static int str9x_erase(struct flash_bank *bank, int first, int last)
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2008-02-25 08:01:21 +00:00
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{
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2009-11-13 18:11:13 +00:00
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struct target *target = bank->target;
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2008-02-25 08:01:21 +00:00
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int i;
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2009-06-18 07:10:25 +00:00
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uint32_t adr;
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2009-06-18 07:06:25 +00:00
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uint8_t status;
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uint8_t erase_cmd;
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2009-06-01 03:05:26 +00:00
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2008-02-28 10:44:41 +00:00
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if (bank->target->state != TARGET_HALTED)
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{
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2008-08-17 19:40:17 +00:00
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LOG_ERROR("Target not halted");
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2008-02-28 10:44:41 +00:00
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return ERROR_TARGET_NOT_HALTED;
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}
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2008-06-05 18:55:55 +00:00
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/* Check if we erase whole bank */
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if ((first == 0) && (last == (bank->num_sectors - 1)))
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{
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/* Optimize to run erase bank command instead of sector */
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erase_cmd = 0x80;
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}
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else
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{
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/* Erase sector command */
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erase_cmd = 0x20;
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}
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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for (i = first; i <= last; i++)
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{
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2008-08-18 17:07:56 +00:00
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int retval;
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2008-02-25 08:01:21 +00:00
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adr = bank->base + bank->sectors[i].offset;
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2009-06-01 03:05:26 +00:00
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2008-02-28 10:44:41 +00:00
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/* erase sectors */
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2009-06-23 22:42:54 +00:00
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if ((retval = target_write_u16(target, adr, erase_cmd)) != ERROR_OK)
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2008-08-18 17:07:56 +00:00
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{
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return retval;
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}
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2009-06-23 22:42:54 +00:00
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if ((retval = target_write_u16(target, adr, 0xD0)) != ERROR_OK)
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2008-08-18 17:07:56 +00:00
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{
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return retval;
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}
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2009-06-01 03:05:26 +00:00
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2008-02-25 08:01:21 +00:00
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/* get status */
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2009-06-23 22:42:54 +00:00
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if ((retval = target_write_u16(target, adr, 0x70)) != ERROR_OK)
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2008-08-18 17:07:56 +00:00
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{
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return retval;
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}
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2008-08-26 11:30:34 +00:00
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2009-06-01 03:05:26 +00:00
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int timeout;
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2009-06-23 22:45:47 +00:00
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for (timeout = 0; timeout < 1000; timeout++) {
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2009-06-23 22:42:54 +00:00
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if ((retval = target_read_u8(target, adr, &status)) != ERROR_OK)
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2008-08-18 17:07:56 +00:00
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{
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return retval;
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}
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2009-06-23 22:47:42 +00:00
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if (status & 0x80)
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2008-02-25 08:01:21 +00:00
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break;
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2008-08-19 16:40:35 +00:00
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alive_sleep(1);
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2008-02-25 08:01:21 +00:00
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}
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2009-06-23 22:42:03 +00:00
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if (timeout == 1000)
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2008-08-26 11:30:34 +00:00
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{
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LOG_ERROR("erase timed out");
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return ERROR_FAIL;
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}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* clear status, also clear read array */
|
2009-06-23 22:42:54 +00:00
|
|
|
if ((retval = target_write_u16(target, adr, 0x50)) != ERROR_OK)
|
2008-08-18 17:07:56 +00:00
|
|
|
{
|
|
|
|
return retval;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* read array command */
|
2009-06-23 22:42:54 +00:00
|
|
|
if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
|
2008-08-18 17:07:56 +00:00
|
|
|
{
|
|
|
|
return retval;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2009-06-23 22:47:42 +00:00
|
|
|
if (status & 0x22)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2008-03-25 15:45:17 +00:00
|
|
|
LOG_ERROR("error erasing flash bank, status: 0x%x", status);
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-06-05 18:55:55 +00:00
|
|
|
/* If we ran erase bank command, we are finished */
|
|
|
|
if (erase_cmd == 0x80)
|
|
|
|
break;
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
for (i = first; i <= last; i++)
|
|
|
|
bank->sectors[i].is_erased = 1;
|
|
|
|
|
|
|
|
return ERROR_OK;
|
|
|
|
}
|
|
|
|
|
2009-11-13 19:32:28 +00:00
|
|
|
static int str9x_protect(struct flash_bank *bank,
|
2009-04-18 10:08:13 +00:00
|
|
|
int set, int first, int last)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2009-11-13 18:11:13 +00:00
|
|
|
struct target *target = bank->target;
|
2008-02-25 08:01:21 +00:00
|
|
|
int i;
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t adr;
|
2009-06-18 07:06:25 +00:00
|
|
|
uint8_t status;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
|
|
{
|
2008-08-17 19:40:17 +00:00
|
|
|
LOG_ERROR("Target not halted");
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
for (i = first; i <= last; i++)
|
|
|
|
{
|
|
|
|
/* Level One Protection */
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
adr = bank->base + bank->sectors[i].offset;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
target_write_u16(target, adr, 0x60);
|
2009-06-23 22:47:42 +00:00
|
|
|
if (set)
|
2008-02-25 08:01:21 +00:00
|
|
|
target_write_u16(target, adr, 0x01);
|
|
|
|
else
|
|
|
|
target_write_u16(target, adr, 0xD0);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* query status */
|
|
|
|
target_read_u8(target, adr, &status);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-04-26 12:50:03 +00:00
|
|
|
/* clear status, also clear read array */
|
|
|
|
target_write_u16(target, adr, 0x50);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-04-26 12:50:03 +00:00
|
|
|
/* read array command */
|
|
|
|
target_write_u16(target, adr, 0xFF);
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_OK;
|
|
|
|
}
|
|
|
|
|
2009-11-13 19:32:28 +00:00
|
|
|
static int str9x_write_block(struct flash_bank *bank,
|
2009-06-18 07:10:25 +00:00
|
|
|
uint8_t *buffer, uint32_t offset, uint32_t count)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2009-11-13 15:39:12 +00:00
|
|
|
struct str9x_flash_bank *str9x_info = bank->driver_priv;
|
2009-11-13 18:11:13 +00:00
|
|
|
struct target *target = bank->target;
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t buffer_size = 8192;
|
2009-11-13 16:44:30 +00:00
|
|
|
struct working_area *source;
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t address = bank->base + offset;
|
2009-11-13 16:39:42 +00:00
|
|
|
struct reg_param reg_params[4];
|
2009-12-05 04:19:49 +00:00
|
|
|
struct arm_algorithm armv4_5_info;
|
2008-06-03 09:46:32 +00:00
|
|
|
int retval = ERROR_OK;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t str9x_flash_write_code[] = {
|
2008-02-25 08:01:21 +00:00
|
|
|
/* write: */
|
|
|
|
0xe3c14003, /* bic r4, r1, #3 */
|
|
|
|
0xe3a03040, /* mov r3, #0x40 */
|
|
|
|
0xe1c430b0, /* strh r3, [r4, #0] */
|
|
|
|
0xe0d030b2, /* ldrh r3, [r0], #2 */
|
|
|
|
0xe0c130b2, /* strh r3, [r1], #2 */
|
|
|
|
0xe3a03070, /* mov r3, #0x70 */
|
|
|
|
0xe1c430b0, /* strh r3, [r4, #0] */
|
|
|
|
/* busy: */
|
|
|
|
0xe5d43000, /* ldrb r3, [r4, #0] */
|
|
|
|
0xe3130080, /* tst r3, #0x80 */
|
|
|
|
0x0afffffc, /* beq busy */
|
|
|
|
0xe3a05050, /* mov r5, #0x50 */
|
|
|
|
0xe1c450b0, /* strh r5, [r4, #0] */
|
|
|
|
0xe3a050ff, /* mov r5, #0xFF */
|
|
|
|
0xe1c450b0, /* strh r5, [r4, #0] */
|
|
|
|
0xe3130012, /* tst r3, #0x12 */
|
|
|
|
0x1a000001, /* bne exit */
|
|
|
|
0xe2522001, /* subs r2, r2, #1 */
|
|
|
|
0x1affffed, /* bne write */
|
|
|
|
/* exit: */
|
|
|
|
0xeafffffe, /* b exit */
|
|
|
|
};
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* flash write code */
|
|
|
|
if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
|
|
|
|
{
|
2008-03-25 15:45:17 +00:00
|
|
|
LOG_WARNING("no working area available, can't do block memory writes");
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
|
|
};
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2009-06-18 07:06:25 +00:00
|
|
|
target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (uint8_t*)str9x_flash_write_code);
|
2008-02-25 08:01:21 +00:00
|
|
|
|
|
|
|
/* memory buffer */
|
|
|
|
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
|
|
|
|
{
|
|
|
|
buffer_size /= 2;
|
|
|
|
if (buffer_size <= 256)
|
|
|
|
{
|
|
|
|
/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
|
|
|
|
if (str9x_info->write_algorithm)
|
|
|
|
target_free_working_area(target, str9x_info->write_algorithm);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-03-25 15:45:17 +00:00
|
|
|
LOG_WARNING("no large enough working area available, can't do block memory writes");
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
|
|
|
}
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2009-12-05 03:46:44 +00:00
|
|
|
armv4_5_info.common_magic = ARM_COMMON_MAGIC;
|
2009-12-05 03:21:14 +00:00
|
|
|
armv4_5_info.core_mode = ARM_MODE_SVC;
|
2009-12-05 03:14:48 +00:00
|
|
|
armv4_5_info.core_state = ARM_STATE_ARM;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
|
|
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
|
|
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
|
|
|
init_reg_param(®_params[3], "r3", 32, PARAM_IN);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
while (count > 0)
|
|
|
|
{
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
target_write_buffer(target, source->address, thisrun_count * 2, buffer);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
buf_set_u32(reg_params[0].value, 0, 32, source->address);
|
|
|
|
buf_set_u32(reg_params[1].value, 0, 32, address);
|
|
|
|
buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
|
|
|
|
|
2009-05-31 09:38:20 +00:00
|
|
|
if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2008-03-25 15:45:17 +00:00
|
|
|
LOG_ERROR("error executing str9x flash write algorithm");
|
2008-06-03 19:36:42 +00:00
|
|
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
2008-06-03 09:46:32 +00:00
|
|
|
break;
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
|
|
|
|
{
|
2008-06-03 09:46:32 +00:00
|
|
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
2008-06-03 19:36:42 +00:00
|
|
|
break;
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
buffer += thisrun_count * 2;
|
|
|
|
address += thisrun_count * 2;
|
|
|
|
count -= thisrun_count;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
target_free_working_area(target, source);
|
|
|
|
target_free_working_area(target, str9x_info->write_algorithm);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
destroy_reg_param(®_params[0]);
|
|
|
|
destroy_reg_param(®_params[1]);
|
|
|
|
destroy_reg_param(®_params[2]);
|
|
|
|
destroy_reg_param(®_params[3]);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-06-03 09:46:32 +00:00
|
|
|
return retval;
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
|
|
|
|
2009-11-13 19:32:28 +00:00
|
|
|
static int str9x_write(struct flash_bank *bank,
|
2009-06-18 07:10:25 +00:00
|
|
|
uint8_t *buffer, uint32_t offset, uint32_t count)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2009-11-13 18:11:13 +00:00
|
|
|
struct target *target = bank->target;
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t words_remaining = (count / 2);
|
|
|
|
uint32_t bytes_remaining = (count & 0x00000001);
|
|
|
|
uint32_t address = bank->base + offset;
|
|
|
|
uint32_t bytes_written = 0;
|
2009-06-18 07:06:25 +00:00
|
|
|
uint8_t status;
|
2009-04-19 08:16:58 +00:00
|
|
|
int retval;
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t check_address = offset;
|
|
|
|
uint32_t bank_adr;
|
2008-02-25 08:01:21 +00:00
|
|
|
int i;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-28 10:44:41 +00:00
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
|
|
{
|
2008-08-17 19:40:17 +00:00
|
|
|
LOG_ERROR("Target not halted");
|
2008-02-28 10:44:41 +00:00
|
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
|
|
}
|
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (offset & 0x1)
|
|
|
|
{
|
2009-06-21 03:22:10 +00:00
|
|
|
LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
for (i = 0; i < bank->num_sectors; i++)
|
|
|
|
{
|
2009-06-18 07:10:25 +00:00
|
|
|
uint32_t sec_start = bank->sectors[i].offset;
|
|
|
|
uint32_t sec_end = sec_start + bank->sectors[i].size;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* check if destination falls within the current sector */
|
|
|
|
if ((check_address >= sec_start) && (check_address < sec_end))
|
|
|
|
{
|
|
|
|
/* check if destination ends in the current sector */
|
|
|
|
if (offset + count < sec_end)
|
|
|
|
check_address = offset + count;
|
|
|
|
else
|
|
|
|
check_address = sec_end;
|
|
|
|
}
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (check_address != offset + count)
|
|
|
|
return ERROR_FLASH_DST_OUT_OF_BANK;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* multiple half words (2-byte) to be programmed? */
|
2009-06-01 03:05:26 +00:00
|
|
|
if (words_remaining > 0)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
|
|
|
/* try using a block write */
|
|
|
|
if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
|
|
|
|
{
|
|
|
|
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
|
|
|
|
{
|
|
|
|
/* if block write failed (no sufficient working area),
|
2009-06-01 03:05:26 +00:00
|
|
|
* we use normal (slow) single dword accesses */
|
2008-03-25 15:45:17 +00:00
|
|
|
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
|
|
|
else if (retval == ERROR_FLASH_OPERATION_FAILED)
|
|
|
|
{
|
2008-03-25 15:45:17 +00:00
|
|
|
LOG_ERROR("flash writing failed with error code: 0x%x", retval);
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
buffer += words_remaining * 2;
|
|
|
|
address += words_remaining * 2;
|
|
|
|
words_remaining = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
while (words_remaining > 0)
|
|
|
|
{
|
|
|
|
bank_adr = address & ~0x03;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* write data command */
|
|
|
|
target_write_u16(target, bank_adr, 0x40);
|
2009-05-31 09:37:57 +00:00
|
|
|
target_write_memory(target, address, 2, 1, buffer + bytes_written);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* get status command */
|
|
|
|
target_write_u16(target, bank_adr, 0x70);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-08-26 11:40:59 +00:00
|
|
|
int timeout;
|
2009-06-23 22:45:47 +00:00
|
|
|
for (timeout = 0; timeout < 1000; timeout++)
|
2009-06-01 03:05:26 +00:00
|
|
|
{
|
2008-02-25 08:01:21 +00:00
|
|
|
target_read_u8(target, bank_adr, &status);
|
2009-06-23 22:47:42 +00:00
|
|
|
if (status & 0x80)
|
2008-02-25 08:01:21 +00:00
|
|
|
break;
|
2008-08-19 16:40:35 +00:00
|
|
|
alive_sleep(1);
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
2009-06-23 22:42:03 +00:00
|
|
|
if (timeout == 1000)
|
2008-08-26 11:30:34 +00:00
|
|
|
{
|
|
|
|
LOG_ERROR("write timed out");
|
|
|
|
return ERROR_FAIL;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* clear status reg and read array */
|
|
|
|
target_write_u16(target, bank_adr, 0x50);
|
|
|
|
target_write_u16(target, bank_adr, 0xFF);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (status & 0x10)
|
|
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
else if (status & 0x02)
|
|
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
|
|
|
|
bytes_written += 2;
|
|
|
|
words_remaining--;
|
|
|
|
address += 2;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (bytes_remaining)
|
|
|
|
{
|
2009-06-18 07:06:25 +00:00
|
|
|
uint8_t last_halfword[2] = {0xff, 0xff};
|
2008-02-25 08:01:21 +00:00
|
|
|
int i = 0;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2009-06-23 22:36:11 +00:00
|
|
|
while (bytes_remaining > 0)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2009-06-01 03:05:26 +00:00
|
|
|
last_halfword[i++] = *(buffer + bytes_written);
|
2008-02-25 08:01:21 +00:00
|
|
|
bytes_remaining--;
|
|
|
|
bytes_written++;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
bank_adr = address & ~0x03;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
|
|
|
/* write data command */
|
2008-02-25 08:01:21 +00:00
|
|
|
target_write_u16(target, bank_adr, 0x40);
|
2009-05-31 09:37:57 +00:00
|
|
|
target_write_memory(target, address, 2, 1, last_halfword);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* query status command */
|
|
|
|
target_write_u16(target, bank_adr, 0x70);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-08-26 11:40:59 +00:00
|
|
|
int timeout;
|
2009-06-23 22:45:47 +00:00
|
|
|
for (timeout = 0; timeout < 1000; timeout++)
|
2009-06-01 03:05:26 +00:00
|
|
|
{
|
2008-02-25 08:01:21 +00:00
|
|
|
target_read_u8(target, bank_adr, &status);
|
2009-06-23 22:47:42 +00:00
|
|
|
if (status & 0x80)
|
2008-02-25 08:01:21 +00:00
|
|
|
break;
|
2008-08-19 16:40:35 +00:00
|
|
|
alive_sleep(1);
|
2008-02-25 08:01:21 +00:00
|
|
|
}
|
2009-06-23 22:42:03 +00:00
|
|
|
if (timeout == 1000)
|
2008-08-26 11:30:34 +00:00
|
|
|
{
|
|
|
|
LOG_ERROR("write timed out");
|
|
|
|
return ERROR_FAIL;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* clear status reg and read array */
|
|
|
|
target_write_u16(target, bank_adr, 0x50);
|
|
|
|
target_write_u16(target, bank_adr, 0xFF);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (status & 0x10)
|
|
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
else if (status & 0x02)
|
|
|
|
return ERROR_FLASH_OPERATION_FAILED;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_OK;
|
|
|
|
}
|
|
|
|
|
2009-11-13 19:32:28 +00:00
|
|
|
static int str9x_probe(struct flash_bank *bank)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
|
|
|
return ERROR_OK;
|
|
|
|
}
|
|
|
|
|
2009-04-18 10:08:13 +00:00
|
|
|
#if 0
|
2009-11-10 07:56:52 +00:00
|
|
|
COMMAND_HANDLER(str9x_handle_part_id_command)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
|
|
|
return ERROR_OK;
|
|
|
|
}
|
2009-04-18 10:08:13 +00:00
|
|
|
#endif
|
2008-02-25 08:01:21 +00:00
|
|
|
|
2009-11-13 19:32:28 +00:00
|
|
|
static int str9x_info(struct flash_bank *bank, char *buf, int buf_size)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2009-06-23 22:47:42 +00:00
|
|
|
snprintf(buf, buf_size, "str9x flash driver info");
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_OK;
|
|
|
|
}
|
|
|
|
|
2009-11-10 07:56:52 +00:00
|
|
|
COMMAND_HANDLER(str9x_handle_flash_config_command)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
2009-11-13 15:39:12 +00:00
|
|
|
struct str9x_flash_bank *str9x_info;
|
2009-11-13 18:11:13 +00:00
|
|
|
struct target *target = NULL;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2009-11-15 12:57:12 +00:00
|
|
|
if (CMD_ARGC < 5)
|
2008-02-25 08:01:21 +00:00
|
|
|
{
|
|
|
|
return ERROR_COMMAND_SYNTAX_ERROR;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2009-11-13 19:32:28 +00:00
|
|
|
struct flash_bank *bank;
|
2009-11-17 21:07:36 +00:00
|
|
|
int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
|
2009-10-23 08:25:22 +00:00
|
|
|
if (ERROR_OK != retval)
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
uint32_t bbsr, nbbsr, bbadr, nbbadr;
|
2009-11-15 16:15:59 +00:00
|
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], bbsr);
|
|
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], nbbsr);
|
|
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], bbadr);
|
|
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], nbbadr);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
str9x_info = bank->driver_priv;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
target = bank->target;
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
if (bank->target->state != TARGET_HALTED)
|
|
|
|
{
|
2008-08-17 19:40:17 +00:00
|
|
|
LOG_ERROR("Target not halted");
|
2008-02-25 08:01:21 +00:00
|
|
|
return ERROR_TARGET_NOT_HALTED;
|
|
|
|
}
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* config flash controller */
|
2009-10-23 08:25:22 +00:00
|
|
|
target_write_u32(target, FLASH_BBSR, bbsr);
|
|
|
|
target_write_u32(target, FLASH_NBBSR, nbbsr);
|
|
|
|
target_write_u32(target, FLASH_BBADR, bbadr >> 2);
|
|
|
|
target_write_u32(target, FLASH_NBBADR, nbbadr >> 2);
|
2008-02-25 08:01:21 +00:00
|
|
|
|
|
|
|
/* set bit 18 instruction TCM order as per flash programming manual */
|
|
|
|
arm966e_write_cp15(target, 62, 0x40000);
|
2009-06-01 03:05:26 +00:00
|
|
|
|
2008-02-25 08:01:21 +00:00
|
|
|
/* enable flash bank 1 */
|
|
|
|
target_write_u32(target, FLASH_CR, 0x18);
|
|
|
|
return ERROR_OK;
|
|
|
|
}
|
2009-11-09 17:20:34 +00:00
|
|
|
|
2009-11-22 12:13:56 +00:00
|
|
|
static const struct command_registration str9x_config_command_handlers[] = {
|
|
|
|
{
|
2010-01-09 16:58:38 +00:00
|
|
|
.name = "flash_config",
|
2009-11-22 12:13:56 +00:00
|
|
|
.handler = &str9x_handle_flash_config_command,
|
|
|
|
.mode = COMMAND_EXEC,
|
2010-01-09 16:58:38 +00:00
|
|
|
.help = "Configure str9x flash controller, prior to "
|
|
|
|
"programming the flash.",
|
|
|
|
.usage = "bank_id BBSR NBBSR BBADR NBBADR",
|
2009-11-22 12:13:56 +00:00
|
|
|
},
|
|
|
|
COMMAND_REGISTRATION_DONE
|
|
|
|
};
|
|
|
|
static const struct command_registration str9x_command_handlers[] = {
|
|
|
|
{
|
|
|
|
.name = "str9x",
|
|
|
|
.mode = COMMAND_ANY,
|
|
|
|
.help = "str9x flash command group",
|
|
|
|
.chain = str9x_config_command_handlers,
|
|
|
|
},
|
|
|
|
COMMAND_REGISTRATION_DONE
|
|
|
|
};
|
|
|
|
|
2009-11-13 15:38:01 +00:00
|
|
|
struct flash_driver str9x_flash = {
|
2009-11-09 17:20:34 +00:00
|
|
|
.name = "str9x",
|
2009-11-22 14:12:04 +00:00
|
|
|
.commands = str9x_command_handlers,
|
2009-11-09 17:20:34 +00:00
|
|
|
.flash_bank_command = &str9x_flash_bank_command,
|
|
|
|
.erase = &str9x_erase,
|
|
|
|
.protect = &str9x_protect,
|
|
|
|
.write = &str9x_write,
|
|
|
|
.probe = &str9x_probe,
|
|
|
|
.auto_probe = &str9x_probe,
|
|
|
|
.erase_check = &default_flash_blank_check,
|
|
|
|
.protect_check = &str9x_protect_check,
|
|
|
|
.info = &str9x_info,
|
|
|
|
};
|