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openocd/src/flash/nor/jtagspi.c

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openocd: src/flash: replace the GPL-2.0-or-later license tag Replace the FSF boilerplate with the SPDX tag. The SPDX tag on files *.c is incorrect, as it should use the C99 single line comment using '//'. But current checkpatch doesn't allow C99 comments, so keep using standard C comments, by now. Change-Id: Ic7db91fe37d1139d42c99e303b3243b6c8fe3ea2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7067 Tested-by: jenkins
2022-06-26 22:53:35 +00:00
/* SPDX-License-Identifier: GPL-2.0-or-later */
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
/***************************************************************************
* Copyright (C) 2015 Robert Jordens <jordens@gmail.com> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "imp.h"
#include <jtag/jtag.h>
#include <flash/nor/spi.h>
#include <helper/time_support.h>
#define JTAGSPI_MAX_TIMEOUT 3000
struct jtagspi_flash_bank {
struct jtag_tap *tap;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
struct flash_device dev;
char devname[32];
flash/nor/jtagspi: Use 'bool' data type Change-Id: I0e81dd476c6b3ec7fee6c84ab1bfcf9bca90c532 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5742 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-01 08:24:35 +00:00
bool probed;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
bool always_4byte; /* use always 4-byte address except for basic read 0x03 */
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
uint32_t ir;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
unsigned int addr_len; /* address length in bytes */
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
};
FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command)
{
struct jtagspi_flash_bank *info;
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
if (CMD_ARGC < 7)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_COMMAND_SYNTAX_ERROR;
info = malloc(sizeof(struct jtagspi_flash_bank));
openocd: fix simple cases of NULL comparison There are more than 1000 NULL comparisons to be aligned to the coding style. For recurrent NULL comparison it's preferable using trivial scripts in order to minimize the review effort. Patch generated automatically with the command: sed -i PATTERN $(find src/ -type f) where PATTERN is in the list: 's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g' Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6350 Tested-by: jenkins
2021-07-03 16:51:20 +00:00
if (!info) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
LOG_ERROR("no memory for flash bank info");
return ERROR_FAIL;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
bank->sectors = NULL;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
bank->driver_priv = info;
info->tap = NULL;
flash/nor/jtagspi: Use 'bool' data type Change-Id: I0e81dd476c6b3ec7fee6c84ab1bfcf9bca90c532 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5742 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-01 08:24:35 +00:00
info->probed = false;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->ir);
return ERROR_OK;
}
static void jtagspi_set_ir(struct flash_bank *bank)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
struct scan_field field;
helper/binarybuffer: fix clang static analyzer warnings Writing bits to an uninitialized buffer generated false warnings. Zero buffers before setting them by buf_set_u32|64() (do it only if bit-by-bit copy loop is used, zeroed buffer is not necessary if a fast path write is used) Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5383 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2019-12-20 22:56:08 +00:00
uint8_t buf[4] = { 0 };
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
LOG_DEBUG("loading jtagspi ir");
buf_set_u32(buf, 0, info->tap->ir_length, info->ir);
field.num_bits = info->tap->ir_length;
field.out_value = buf;
field.in_value = NULL;
jtag_add_ir_scan(info->tap, &field, TAP_IDLE);
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
static void flip_u8(const uint8_t *in, uint8_t *out, unsigned int len)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
{
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
for (unsigned int i = 0; i < len; i++)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
out[i] = flip_u32(in[i], 8);
}
static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
uint8_t *write_buffer, unsigned int write_len, uint8_t *data_buffer, int data_len)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
{
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
assert(write_buffer || write_len == 0);
assert(data_buffer || data_len == 0);
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
struct scan_field fields[6];
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
LOG_DEBUG("cmd=0x%02x write_len=%d data_len=%d", cmd, write_len, data_len);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
/* negative data_len == read operation */
const bool is_read = (data_len < 0);
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
if (is_read)
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
data_len = -data_len;
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
int n = 0;
const uint8_t marker = 1;
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
fields[n].num_bits = 1;
fields[n].out_value = &marker;
fields[n].in_value = NULL;
n++;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
/* transfer length = cmd + address + read/write,
* -1 due to the counter implementation */
uint8_t xfer_bits[4];
h_u32_to_be(xfer_bits, ((sizeof(cmd) + write_len + data_len) * CHAR_BIT) - 1);
flip_u8(xfer_bits, xfer_bits, sizeof(xfer_bits));
fields[n].num_bits = sizeof(xfer_bits) * CHAR_BIT;
fields[n].out_value = xfer_bits;
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
fields[n].in_value = NULL;
n++;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
flip_u8(&cmd, &cmd, sizeof(cmd));
fields[n].num_bits = sizeof(cmd) * CHAR_BIT;
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
fields[n].out_value = &cmd;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
fields[n].in_value = NULL;
n++;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
if (write_len) {
flip_u8(write_buffer, write_buffer, write_len);
fields[n].num_bits = write_len * CHAR_BIT;
fields[n].out_value = write_buffer;
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
fields[n].in_value = NULL;
n++;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
if (data_len > 0) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if (is_read) {
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
fields[n].num_bits = jtag_tap_count_enabled();
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
fields[n].out_value = NULL;
fields[n].in_value = NULL;
n++;
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
fields[n].out_value = NULL;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
fields[n].in_value = data_buffer;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
} else {
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
flip_u8(data_buffer, data_buffer, data_len);
fields[n].out_value = data_buffer;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
fields[n].in_value = NULL;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
fields[n].num_bits = data_len * CHAR_BIT;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
n++;
}
jtagspi_set_ir(bank);
jtagspi: new protocol that includes transfer length This commit contains a rewrite of the jtagspi protocol and covers both changes in the jtagspi.c openocd driver and the bscan_spi (xilinx_bscan_spi) proxy bitstreams. The changes are as follows: 1. Always perform IR scan to ensure proper clearing of BYPASSed DRs. 2. Insert alignment cycles for all BYPASSed TAPs: The previous logic was erroneous. The delay in clock cyles from a bit written to the jtag interface to a bit read by the jtag interface is: * The number of BYPASSed TAPs before this (jtagspi) tap * The length of the jtagspi data register (1) * The number of BYPASSed TAPs before this one. I.e. it is just the number of enabled TAPs. This also gets rid of the configuration parameter DR_LENGTH. 3. Use marker bit to start spi transfer If there are TAPs ahead of this one on the JTAG chain, and we are in DR-SHIFT, there will be old bits toggled through first before the first valid bit destined for the flash. This delays the begin of the JTAGSPI transaction until the first high bit. 4. New jtagspi protocol A JTAGSPI transfer now consists of: * an arbitrary number of 0 bits (from BYPASS registers in front of the JTAG2SPI DR) * a marker bit (1) indicating the start of the JTAG2SPI transaction * 32 bits (big endian) describing the length of the SPI transaction * a number of SPI clock cycles (corresponding to 3.) with CS_N asserted * an arbitrary number of cycles (to shift MISO/TDO data through subsequent BYPASS registers) 5. xilinx_bscan_spi: clean up, add ultrascale This is tested on the following configurations: * KC705: XC7K325T * Sayma AMC: XCKU040 * Sayma AMC + RTM): XCKU040 + XC7A15T, a board with integrated FTDI JTAG adapter, SCANSTA JTAG router, a Xilinx Ultrascale XCKU040 and a Xilinx Artix 7 15T. https://github.com/m-labs/sinara/wiki/Sayma * Custom board with Lattice FPGA + XC7A35T * CUstom board with 3x XCKU115-2FLVA1517E Change-Id: I7361e9fb284ebb916302941735eebef3612aa103 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/4236 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-08-08 16:16:35 +00:00
/* passing from an IR scan to SHIFT-DR clears BYPASS registers */
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
struct jtagspi_flash_bank *info = bank->driver_priv;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
jtag_add_dr_scan(info->tap, n, fields, TAP_IDLE);
flash/nor/jtagspi: propagate error from jtag_execute_queue() Change-Id: Ib985bdf3d60345a1e701f9cc98f89a47ff74d3e2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5684 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-17 06:17:25 +00:00
int retval = jtag_execute_queue();
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if (is_read)
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
flip_u8(data_buffer, data_buffer, data_len);
flash/nor/jtagspi: propagate error from jtag_execute_queue() Change-Id: Ib985bdf3d60345a1e701f9cc98f89a47ff74d3e2 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5684 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-05-17 06:17:25 +00:00
return retval;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
COMMAND_HANDLER(jtagspi_handle_set)
{
struct flash_bank *bank = NULL;
struct jtagspi_flash_bank *info = NULL;
struct flash_sector *sectors = NULL;
uint32_t temp;
unsigned int index = 1;
int retval;
LOG_DEBUG("%s", __func__);
/* there are 6 mandatory arguments:
* devname, size_in_bytes, pagesize, read_cmd, unused, pprog_cmd */
if (index + 6 > CMD_ARGC) {
command_print(CMD, "jtagspi: not enough arguments");
return ERROR_COMMAND_SYNTAX_ERROR;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
info = bank->driver_priv;
/* invalidate all old info */
if (info->probed) {
bank->size = 0;
bank->num_sectors = 0;
if (bank->sectors)
free(bank->sectors);
bank->sectors = NULL;
info->always_4byte = false;
info->probed = false;
}
memset(&info->dev, 0, sizeof(info->dev));
strncpy(info->devname, CMD_ARGV[index++], sizeof(info->devname) - 1);
info->devname[sizeof(info->devname) - 1] = '\0';
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], temp);
info->dev.size_in_bytes = temp;
if ((temp & (temp - 1)) || (temp < (1UL << 8))) {
command_print(CMD, "jtagspi: device size must be 2^n with n >= 8");
return ERROR_COMMAND_SYNTAX_ERROR;
}
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], temp);
info->dev.pagesize = temp;
if (info->dev.pagesize == 0)
info->dev.pagesize = SPIFLASH_DEF_PAGESIZE;
if ((temp & (temp - 1)) || (temp > info->dev.size_in_bytes)) {
command_print(CMD, "jtagspi: page size must be 2^n and <= device size");
return ERROR_COMMAND_SYNTAX_ERROR;
}
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], info->dev.read_cmd);
if ((info->dev.read_cmd != 0x03) &&
(info->dev.read_cmd != 0x13)) {
command_print(CMD, "jtagspi: only 0x03/0x13 READ allowed");
return ERROR_COMMAND_SYNTAX_ERROR;
}
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], info->dev.qread_cmd);
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], info->dev.pprog_cmd);
if ((info->dev.pprog_cmd != 0x02) &&
(info->dev.pprog_cmd != 0x12)) {
command_print(CMD, "jtagspi: only 0x02/0x12 PPRG allowed");
return ERROR_COMMAND_SYNTAX_ERROR;
}
/* remaining params are optional */
if (index < CMD_ARGC)
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], info->dev.chip_erase_cmd);
else
info->dev.chip_erase_cmd = 0x00;
if (index < CMD_ARGC) {
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[index++], temp);
info->dev.sectorsize = temp;
if ((info->dev.sectorsize > info->dev.size_in_bytes) ||
(info->dev.sectorsize < info->dev.pagesize) || (temp & (temp - 1))) {
command_print(CMD, "jtagspi: sector size must be 2^n and <= device size");
return ERROR_COMMAND_SYNTAX_ERROR;
}
if (index < CMD_ARGC)
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], info->dev.erase_cmd);
else {
command_print(CMD, "jtagspi: erase command missing");
return ERROR_COMMAND_SYNTAX_ERROR;
}
} else {
/* no sector size / sector erase cmd given, treat whole bank as a single sector */
info->dev.erase_cmd = 0x00;
info->dev.sectorsize = info->dev.size_in_bytes;
}
if (index < CMD_ARGC) {
command_print(CMD, "jtagspi: extra arguments");
return ERROR_COMMAND_SYNTAX_ERROR;
}
/* set correct size value */
bank->size = info->dev.size_in_bytes;
/* calculate address length in bytes */
if (bank->size <= (1UL << 8))
info->addr_len = 1;
else if (bank->size <= (1UL << 16))
info->addr_len = 2;
else if (bank->size <= (1UL << 24))
info->addr_len = 3;
else {
info->addr_len = 4;
LOG_WARNING("4-byte addresses needed, might need extra command to enable");
}
/* create and fill sectors array */
bank->num_sectors =
info->dev.size_in_bytes / info->dev.sectorsize;
sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
if (!sectors) {
LOG_ERROR("Not enough memory");
return ERROR_FAIL;
}
for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
sectors[sector].offset = sector * (info->dev.sectorsize);
sectors[sector].size = info->dev.sectorsize;
sectors[sector].is_erased = -1;
sectors[sector].is_protected = 0;
}
bank->sectors = sectors;
info->dev.name = info->devname;
if (info->dev.size_in_bytes / 4096)
LOG_INFO("flash \'%s\' id = unknown\nflash size = %" PRIu32 " kbytes",
info->dev.name, info->dev.size_in_bytes / 1024);
else
LOG_INFO("flash \'%s\' id = unknown\nflash size = %" PRIu32 " bytes",
info->dev.name, info->dev.size_in_bytes);
info->probed = true;
return ERROR_OK;
}
COMMAND_HANDLER(jtagspi_handle_cmd)
{
struct flash_bank *bank;
unsigned int index = 1;
const int max = 21;
uint8_t num_write, num_read, write_buffer[max], read_buffer[1 << CHAR_BIT];
uint8_t data, *ptr;
char temp[4], output[(2 + max + (1 << CHAR_BIT)) * 3 + 8];
int retval;
LOG_DEBUG("%s", __func__);
if (CMD_ARGC < 3) {
command_print(CMD, "jtagspi: not enough arguments");
return ERROR_COMMAND_SYNTAX_ERROR;
}
num_write = CMD_ARGC - 2;
if (num_write > max) {
LOG_ERROR("at most %d bytes may be send", max);
return ERROR_COMMAND_SYNTAX_ERROR;
}
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index++], num_read);
snprintf(output, sizeof(output), "spi: ");
for (ptr = &write_buffer[0] ; index < CMD_ARGC; index++) {
COMMAND_PARSE_NUMBER(u8, CMD_ARGV[index], data);
*ptr++ = data;
snprintf(temp, sizeof(temp), "%02" PRIx8 " ", data);
strncat(output, temp, sizeof(output) - strlen(output) - 1);
}
strncat(output, "-> ", sizeof(output) - strlen(output) - 1);
/* process command */
ptr = &read_buffer[0];
jtagspi_cmd(bank, write_buffer[0], &write_buffer[1], num_write - 1, ptr, -num_read);
if (retval != ERROR_OK)
return retval;
for ( ; num_read > 0; num_read--) {
snprintf(temp, sizeof(temp), "%02" PRIx8 " ", *ptr++);
strncat(output, temp, sizeof(output) - strlen(output) - 1);
}
command_print(CMD, "%s", output);
return ERROR_OK;
}
COMMAND_HANDLER(jtagspi_handle_always_4byte)
{
struct flash_bank *bank;
struct jtagspi_flash_bank *jtagspi_info;
int retval;
LOG_DEBUG("%s", __func__);
if ((CMD_ARGC != 1) && (CMD_ARGC != 2))
return ERROR_COMMAND_SYNTAX_ERROR;
retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
if (ERROR_OK != retval)
return retval;
jtagspi_info = bank->driver_priv;
if (CMD_ARGC == 1)
command_print(CMD, jtagspi_info->always_4byte ? "on" : "off");
else
COMMAND_PARSE_BOOL(CMD_ARGV[1], jtagspi_info->always_4byte, "on", "off");
return ERROR_OK;
}
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
static int jtagspi_probe(struct flash_bank *bank)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
struct flash_sector *sectors;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
const struct flash_device *p;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
uint8_t in_buf[3];
SPI table updates (some new devices and new info) read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices use variants for 4-byte addressing. Some new flash and FRAM device ids added. FRAMs don't have write pages nor erase commands or sector sizes. The corresponding entries are marked as "not used" (i. e. zero). Checks in existing SPI flash drivers added to handle these cases gracefully. Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4773 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-18 16:08:20 +00:00
uint32_t id, sectorsize;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
if (bank->sectors) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
free(bank->sectors);
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
bank->sectors = NULL;
}
flash/nor/jtagspi: Use 'bool' data type Change-Id: I0e81dd476c6b3ec7fee6c84ab1bfcf9bca90c532 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5742 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-01 08:24:35 +00:00
info->probed = false;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
openocd: remove NULL comparisons with checkpatch [1/2] Patch generated automatically through the new checkpatch with flags "--types COMPARISON_TO_NULL --fix-inplace". This only fixes the comparisons if (symbol == NULL) if (symbol != NULL) The case of NULL on the left side of the comparison is not tested. Some automatic fix is incorrect and has been massaged by hands: - if (*psig == NULL) + if (*!psig) changed as + if (!*psig) Change-Id: If4a1e2b4e547e223532e8e3d9da89bf9cb382ce6 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6351 Tested-by: jenkins
2021-07-03 19:29:32 +00:00
if (!bank->target->tap) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
LOG_ERROR("Target has no JTAG tap");
return ERROR_FAIL;
}
info->tap = bank->target->tap;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
jtagspi_cmd(bank, SPIFLASH_READ_ID, NULL, 0, in_buf, -3);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
/* the table in spi.c has the manufacturer byte (first) as the lsb */
id = le_to_h_u24(in_buf);
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
memset(&info->dev, 0, sizeof(info->dev));
for (p = flash_devices; p->name ; p++)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if (p->device_id == id) {
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
memcpy(&info->dev, p, sizeof(info->dev));
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
break;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
if (!(p->name)) {
LOG_ERROR("Unknown flash device (ID 0x%06" PRIx32 ")", id & 0xFFFFFF);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_FAIL;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
LOG_INFO("Found flash device \'%s\' (ID 0x%06" PRIx32 ")",
info->dev.name, info->dev.device_id & 0xFFFFFF);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
/* Set correct size value */
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
bank->size = info->dev.size_in_bytes;
/* calculate address length in bytes */
if (bank->size <= (1UL << 8))
info->addr_len = 1;
else if (bank->size <= (1UL << 16))
info->addr_len = 2;
else if (bank->size <= (1UL << 24))
info->addr_len = 3;
else {
info->addr_len = 4;
LOG_WARNING("4-byte addresses needed, might need extra command to enable");
}
SPI table updates (some new devices and new info) read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices use variants for 4-byte addressing. Some new flash and FRAM device ids added. FRAMs don't have write pages nor erase commands or sector sizes. The corresponding entries are marked as "not used" (i. e. zero). Checks in existing SPI flash drivers added to handle these cases gracefully. Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4773 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-18 16:08:20 +00:00
/* if no sectors, treat whole bank as single sector */
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
sectorsize = info->dev.sectorsize ?
info->dev.sectorsize : info->dev.size_in_bytes;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
/* create and fill sectors array */
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
bank->num_sectors = info->dev.size_in_bytes / sectorsize;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
openocd: fix simple cases of NULL comparison There are more than 1000 NULL comparisons to be aligned to the coding style. For recurrent NULL comparison it's preferable using trivial scripts in order to minimize the review effort. Patch generated automatically with the command: sed -i PATTERN $(find src/ -type f) where PATTERN is in the list: 's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g' 's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g' 's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g' Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6350 Tested-by: jenkins
2021-07-03 16:51:20 +00:00
if (!sectors) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
LOG_ERROR("not enough memory");
return ERROR_FAIL;
}
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
SPI table updates (some new devices and new info) read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices use variants for 4-byte addressing. Some new flash and FRAM device ids added. FRAMs don't have write pages nor erase commands or sector sizes. The corresponding entries are marked as "not used" (i. e. zero). Checks in existing SPI flash drivers added to handle these cases gracefully. Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4773 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-18 16:08:20 +00:00
sectors[sector].offset = sector * sectorsize;
sectors[sector].size = sectorsize;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
sectors[sector].is_erased = -1;
sectors[sector].is_protected = 0;
}
bank->sectors = sectors;
flash/nor/jtagspi: Use 'bool' data type Change-Id: I0e81dd476c6b3ec7fee6c84ab1bfcf9bca90c532 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/5742 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-07-01 08:24:35 +00:00
info->probed = true;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_OK;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
static int jtagspi_auto_probe(struct flash_bank *bank)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
if (info->probed)
return ERROR_OK;
return jtagspi_probe(bank);
}
flash: nor: jtagspi: make read_status report errors This is a follow-up to 3c9bd7c6f30a34e3930e44dd2e8ce5f5a877b4eb. Change-Id: If430f7fcfbba084d9cd74b32344ad43508a96a77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4383 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-30 09:17:33 +00:00
static int jtagspi_read_status(struct flash_bank *bank, uint32_t *status)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
{
uint8_t buf;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
int err = jtagspi_cmd(bank, SPIFLASH_READ_STATUS, NULL, 0, &buf, -1);
flash: nor: jtagspi: make read_status report errors This is a follow-up to 3c9bd7c6f30a34e3930e44dd2e8ce5f5a877b4eb. Change-Id: If430f7fcfbba084d9cd74b32344ad43508a96a77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4383 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-30 09:17:33 +00:00
if (err == ERROR_OK) {
flash: nor: jtagspi: fix jtagspi_read_status() warning Clang static analyzer says that in certain cases "Assigned value is garbage or undefined" there. Change-Id: Ib35a4cf7a553ba9461270a0dc4c4b9b205091e73 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4338 Tested-by: jenkins
2018-01-14 16:28:20 +00:00
*status = buf;
jtagspi: fix build on MacOS Commit be57b0ab847e ("Update jtagspi driver for 1-, 2- and 4-byte addresses") introduces two incorrect format string for uint32_t data types. This cause build failure on MacOS: src/flash/nor/jtagspi.c:474:35: error: format specifies type 'unsigned char' but the argument has type 'uint32_t' (aka 'unsigned int') [-Werror,-Wformat] LOG_DEBUG("status=0x%02" PRIx8, *status); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ src/flash/nor/jtagspi.c:513:65: error: format specifies type 'unsigned char' but the argument has type 'uint32_t' (aka 'unsigned int') [-Werror,-Wformat] LOG_ERROR("Cannot enable write to flash. Status=0x%02" PRIx8, status); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ Fix the format string. Change-Id: I209053317c8b26c35c6f11be0553ccccc698c551 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: be57b0ab847e ("Update jtagspi driver for 1-, 2- and 4-byte addresses") Reviewed-on: https://review.openocd.org/c/openocd/+/6701 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-11-13 13:38:21 +00:00
LOG_DEBUG("status=0x%02" PRIx32, *status);
flash: nor: jtagspi: fix jtagspi_read_status() warning Clang static analyzer says that in certain cases "Assigned value is garbage or undefined" there. Change-Id: Ib35a4cf7a553ba9461270a0dc4c4b9b205091e73 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4338 Tested-by: jenkins
2018-01-14 16:28:20 +00:00
}
flash: nor: jtagspi: make read_status report errors This is a follow-up to 3c9bd7c6f30a34e3930e44dd2e8ce5f5a877b4eb. Change-Id: If430f7fcfbba084d9cd74b32344ad43508a96a77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4383 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-30 09:17:33 +00:00
return err;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
}
static int jtagspi_wait(struct flash_bank *bank, int timeout_ms)
{
Fix usage of timeval_ms() First, fix the timeval_ms() implementation to not have K&R but ANSI argument semantics by adding a missing void. timeval_ms() returns an int64_t, not uint64_t or long long. Consistently use int64_t for variables and PRI*64 as format string. While at it, change a few related variables to bool for clarity. Note that timeval_ms() may return a negative error code, but not a single caller checks for that. Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3499 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-22 02:34:04 +00:00
int64_t t0 = timeval_ms();
int64_t dt;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
do {
dt = timeval_ms() - t0;
flash: nor: jtagspi: make read_status report errors This is a follow-up to 3c9bd7c6f30a34e3930e44dd2e8ce5f5a877b4eb. Change-Id: If430f7fcfbba084d9cd74b32344ad43508a96a77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4383 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-30 09:17:33 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
uint32_t status = (uint32_t)-1;
flash: nor: jtagspi: make read_status report errors This is a follow-up to 3c9bd7c6f30a34e3930e44dd2e8ce5f5a877b4eb. Change-Id: If430f7fcfbba084d9cd74b32344ad43508a96a77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4383 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-30 09:17:33 +00:00
int retval = jtagspi_read_status(bank, &status);
if (retval != ERROR_OK)
return retval;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if ((status & SPIFLASH_BSY_BIT) == 0) {
Fix usage of timeval_ms() First, fix the timeval_ms() implementation to not have K&R but ANSI argument semantics by adding a missing void. timeval_ms() returns an int64_t, not uint64_t or long long. Consistently use int64_t for variables and PRI*64 as format string. While at it, change a few related variables to bool for clarity. Note that timeval_ms() may return a negative error code, but not a single caller checks for that. Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3499 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-22 02:34:04 +00:00
LOG_DEBUG("waited %" PRId64 " ms", dt);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_OK;
}
alive_sleep(1);
} while (dt <= timeout_ms);
LOG_ERROR("timeout, device still busy");
return ERROR_FAIL;
}
static int jtagspi_write_enable(struct flash_bank *bank)
{
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
jtagspi_cmd(bank, SPIFLASH_WRITE_ENABLE, NULL, 0, NULL, 0);
flash: nor: jtagspi: make read_status report errors This is a follow-up to 3c9bd7c6f30a34e3930e44dd2e8ce5f5a877b4eb. Change-Id: If430f7fcfbba084d9cd74b32344ad43508a96a77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4383 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-30 09:17:33 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
uint32_t status = (uint32_t)-1;
flash: nor: jtagspi: make read_status report errors This is a follow-up to 3c9bd7c6f30a34e3930e44dd2e8ce5f5a877b4eb. Change-Id: If430f7fcfbba084d9cd74b32344ad43508a96a77 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4383 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-30 09:17:33 +00:00
int retval = jtagspi_read_status(bank, &status);
if (retval != ERROR_OK)
return retval;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if ((status & SPIFLASH_WE_BIT) == 0) {
jtagspi: fix build on MacOS Commit be57b0ab847e ("Update jtagspi driver for 1-, 2- and 4-byte addresses") introduces two incorrect format string for uint32_t data types. This cause build failure on MacOS: src/flash/nor/jtagspi.c:474:35: error: format specifies type 'unsigned char' but the argument has type 'uint32_t' (aka 'unsigned int') [-Werror,-Wformat] LOG_DEBUG("status=0x%02" PRIx8, *status); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ src/flash/nor/jtagspi.c:513:65: error: format specifies type 'unsigned char' but the argument has type 'uint32_t' (aka 'unsigned int') [-Werror,-Wformat] LOG_ERROR("Cannot enable write to flash. Status=0x%02" PRIx8, status); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ Fix the format string. Change-Id: I209053317c8b26c35c6f11be0553ccccc698c551 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Fixes: be57b0ab847e ("Update jtagspi driver for 1-, 2- and 4-byte addresses") Reviewed-on: https://review.openocd.org/c/openocd/+/6701 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
2021-11-13 13:38:21 +00:00
LOG_ERROR("Cannot enable write to flash. Status=0x%02" PRIx32, status);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_FAIL;
}
return ERROR_OK;
}
static int jtagspi_bulk_erase(struct flash_bank *bank)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
int retval;
Fix usage of timeval_ms() First, fix the timeval_ms() implementation to not have K&R but ANSI argument semantics by adding a missing void. timeval_ms() returns an int64_t, not uint64_t or long long. Consistently use int64_t for variables and PRI*64 as format string. While at it, change a few related variables to bool for clarity. Note that timeval_ms() may return a negative error code, but not a single caller checks for that. Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3499 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-22 02:34:04 +00:00
int64_t t0 = timeval_ms();
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
if (info->dev.chip_erase_cmd == 0x00)
SPI table updates (some new devices and new info) read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices use variants for 4-byte addressing. Some new flash and FRAM device ids added. FRAMs don't have write pages nor erase commands or sector sizes. The corresponding entries are marked as "not used" (i. e. zero). Checks in existing SPI flash drivers added to handle these cases gracefully. Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4773 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-18 16:08:20 +00:00
return ERROR_FLASH_OPER_UNSUPPORTED;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
retval = jtagspi_write_enable(bank);
if (retval != ERROR_OK)
return retval;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
jtagspi_cmd(bank, info->dev.chip_erase_cmd, NULL, 0, NULL, 0);
if (retval != ERROR_OK)
return retval;
retval = jtagspi_wait(bank, bank->num_sectors * JTAGSPI_MAX_TIMEOUT);
Fix usage of timeval_ms() First, fix the timeval_ms() implementation to not have K&R but ANSI argument semantics by adding a missing void. timeval_ms() returns an int64_t, not uint64_t or long long. Consistently use int64_t for variables and PRI*64 as format string. While at it, change a few related variables to bool for clarity. Note that timeval_ms() may return a negative error code, but not a single caller checks for that. Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3499 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-22 02:34:04 +00:00
LOG_INFO("took %" PRId64 " ms", timeval_ms() - t0);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return retval;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
static uint8_t *fill_addr(uint32_t addr, unsigned int addr_len, uint8_t *buffer)
{
for (buffer += addr_len; addr_len > 0; --addr_len) {
*--buffer = addr;
addr >>= 8;
}
return buffer;
}
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
static int jtagspi_sector_erase(struct flash_bank *bank, unsigned int sector)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
{
struct jtagspi_flash_bank *info = bank->driver_priv;
int retval;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
uint8_t addr[sizeof(uint32_t)];
Fix usage of timeval_ms() First, fix the timeval_ms() implementation to not have K&R but ANSI argument semantics by adding a missing void. timeval_ms() returns an int64_t, not uint64_t or long long. Consistently use int64_t for variables and PRI*64 as format string. While at it, change a few related variables to bool for clarity. Note that timeval_ms() may return a negative error code, but not a single caller checks for that. Change-Id: I27cf83e75b3e9a8913f6c43e98a281bea77aac13 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3499 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-05-22 02:34:04 +00:00
int64_t t0 = timeval_ms();
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
retval = jtagspi_write_enable(bank);
if (retval != ERROR_OK)
return retval;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
/* ATXP032/064/128 use always 4-byte addresses except for 0x03 read */
unsigned int addr_len = info->always_4byte ? 4 : info->addr_len;
retval = jtagspi_cmd(bank, info->dev.erase_cmd, fill_addr(bank->sectors[sector].offset, addr_len, addr),
addr_len, NULL, 0);
if (retval != ERROR_OK)
return retval;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
retval = jtagspi_wait(bank, JTAGSPI_MAX_TIMEOUT);
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
LOG_INFO("sector %u took %" PRId64 " ms", sector, timeval_ms() - t0);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return retval;
}
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
static int jtagspi_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
{
struct jtagspi_flash_bank *info = bank->driver_priv;
flash/nor/jtagspi: 'retval' may be used uninitialized Problem As my compiler has "warnings being treated as errors" on, it shows the error message: error: 'retval' may be used uninitialized in this function Investigation Nothing wrong with the logic, 'retval' would have a value before returning. Just wanna get rid of the compiling "warning as error" message. Solution Provide a reasonable default value Change-Id: I712c15f82819c6c48bee9dceca8de4b18aeb29b0 Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2905 Tested-by: jenkins Reviewed-by: Robert Jordens <jordens@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-08-06 21:45:19 +00:00
int retval = ERROR_OK;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
LOG_DEBUG("erase from sector %u to sector %u", first, last);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
if ((last < first) || (last >= bank->num_sectors)) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
LOG_ERROR("Flash sector invalid");
return ERROR_FLASH_SECTOR_INVALID;
}
if (!(info->probed)) {
LOG_ERROR("Flash bank not probed");
return ERROR_FLASH_BANK_NOT_PROBED;
}
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
for (unsigned int sector = first; sector <= last; sector++) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if (bank->sectors[sector].is_protected) {
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
LOG_ERROR("Flash sector %u protected", sector);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_FAIL;
}
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
if (first == 0 && last == (bank->num_sectors - 1) &&
info->dev.chip_erase_cmd != 0x00 &&
info->dev.chip_erase_cmd != info->dev.erase_cmd) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
LOG_DEBUG("Trying bulk erase.");
retval = jtagspi_bulk_erase(bank);
if (retval == ERROR_OK)
return retval;
else
LOG_WARNING("Bulk flash erase failed. Falling back to sector erase.");
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
if (info->dev.erase_cmd == 0x00)
SPI table updates (some new devices and new info) read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices use variants for 4-byte addressing. Some new flash and FRAM device ids added. FRAMs don't have write pages nor erase commands or sector sizes. The corresponding entries are marked as "not used" (i. e. zero). Checks in existing SPI flash drivers added to handle these cases gracefully. Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4773 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-18 16:08:20 +00:00
return ERROR_FLASH_OPER_UNSUPPORTED;
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
for (unsigned int sector = first; sector <= last; sector++) {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
retval = jtagspi_sector_erase(bank, sector);
if (retval != ERROR_OK) {
LOG_ERROR("Sector erase failed.");
break;
}
}
return retval;
}
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
static int jtagspi_protect(struct flash_bank *bank, int set, unsigned int first,
unsigned int last)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
{
flash/nor: Use proper data types in driver API Use 'unsigned int' and 'bool' instead of 'int' where appropriate. While at it, fix some coding style issues. No new Clang analyzer warnings. Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8 Signed-off-by: Marc Schink <dev@zapb.de> Reviewed-on: http://openocd.zylin.com/4929 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2020-06-07 15:00:13 +00:00
for (unsigned int sector = first; sector <= last; sector++)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
bank->sectors[sector].is_protected = set;
return ERROR_OK;
}
static int jtagspi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
uint32_t pagesize, currsize;
uint8_t addr[sizeof(uint32_t)];
int retval;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if (!(info->probed)) {
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
LOG_ERROR("Flash bank not probed.");
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_FLASH_BANK_NOT_PROBED;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
/* if no sectorsize, use reasonable default */
pagesize = info->dev.sectorsize ? info->dev.sectorsize : info->dev.pagesize;
if (pagesize == 0)
pagesize = (info->dev.size_in_bytes <= SPIFLASH_DEF_PAGESIZE) ?
info->dev.size_in_bytes : SPIFLASH_DEF_PAGESIZE;
/* ATXP032/064/128 use always 4-byte addresses except for 0x03 read */
unsigned int addr_len = ((info->dev.read_cmd != 0x03) && info->always_4byte) ? 4 : info->addr_len;
while (count > 0) {
/* length up to end of current page */
currsize = ((offset + pagesize) & ~(pagesize - 1)) - offset;
/* but no more than remaining size */
currsize = (count < currsize) ? count : currsize;
retval = jtagspi_cmd(bank, info->dev.read_cmd, fill_addr(offset, addr_len, addr),
addr_len, buffer, -currsize);
if (retval != ERROR_OK) {
LOG_ERROR("page read error");
return retval;
}
LOG_DEBUG("read page at 0x%08" PRIx32, offset);
offset += currsize;
buffer += currsize;
count -= currsize;
}
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_OK;
}
static int jtagspi_page_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
{
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
struct jtagspi_flash_bank *info = bank->driver_priv;
uint8_t addr[sizeof(uint32_t)];
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
int retval;
retval = jtagspi_write_enable(bank);
if (retval != ERROR_OK)
return retval;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
/* ATXP032/064/128 use always 4-byte addresses except for 0x03 read */
unsigned int addr_len = ((info->dev.read_cmd != 0x03) && info->always_4byte) ? 4 : info->addr_len;
retval = jtagspi_cmd(bank, info->dev.pprog_cmd, fill_addr(offset, addr_len, addr),
addr_len, (uint8_t *) buffer, count);
if (retval != ERROR_OK)
return retval;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return jtagspi_wait(bank, JTAGSPI_MAX_TIMEOUT);
}
static int jtagspi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
uint32_t pagesize, currsize;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
int retval;
if (!(info->probed)) {
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
LOG_ERROR("Flash bank not probed.");
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_FLASH_BANK_NOT_PROBED;
}
SPI table updates (some new devices and new info) read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices use variants for 4-byte addressing. Some new flash and FRAM device ids added. FRAMs don't have write pages nor erase commands or sector sizes. The corresponding entries are marked as "not used" (i. e. zero). Checks in existing SPI flash drivers added to handle these cases gracefully. Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4773 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-18 16:08:20 +00:00
/* if no write pagesize, use reasonable default */
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
pagesize = info->dev.pagesize ? info->dev.pagesize : SPIFLASH_DEF_PAGESIZE;
while (count > 0) {
/* length up to end of current page */
currsize = ((offset + pagesize) & ~(pagesize - 1)) - offset;
/* but no more than remaining size */
currsize = (count < currsize) ? count : currsize;
SPI table updates (some new devices and new info) read_cmd, qread_cmd, pprog_cmd added as some recent high densities devices use variants for 4-byte addressing. Some new flash and FRAM device ids added. FRAMs don't have write pages nor erase commands or sector sizes. The corresponding entries are marked as "not used" (i. e. zero). Checks in existing SPI flash drivers added to handle these cases gracefully. Change-Id: I5104bce7c815ac22f98bc32c1bb6db66b984404a Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: http://openocd.zylin.com/4773 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-18 16:08:20 +00:00
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
retval = jtagspi_page_write(bank, buffer, offset, currsize);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
if (retval != ERROR_OK) {
LOG_ERROR("page write error");
return retval;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
LOG_DEBUG("wrote page at 0x%08" PRIx32, offset);
offset += currsize;
buffer += currsize;
count -= currsize;
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
}
return ERROR_OK;
}
flash/nor: improved API of flash_driver.info & fixed buffer overruns 1) The API of "info" callback in "struct flash_driver" has been improved. Fixed buffers for strings 2) Removed the calls to snprintf() from the flash_driver.info implementations. Many of them were used in an unsafe manner (buffer overruns were possible). Change-Id: I42ab8a8018d01f9af43c5ba49f650c3cb5d31dcb Signed-off-by: Jan Matyas <matyas@codasip.com> Reviewed-on: http://openocd.zylin.com/6182 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-04-23 08:47:17 +00:00
static int jtagspi_info(struct flash_bank *bank, struct command_invocation *cmd)
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
{
struct jtagspi_flash_bank *info = bank->driver_priv;
if (!(info->probed)) {
flash/nor: improved API of flash_driver.info & fixed buffer overruns 1) The API of "info" callback in "struct flash_driver" has been improved. Fixed buffers for strings 2) Removed the calls to snprintf() from the flash_driver.info implementations. Many of them were used in an unsafe manner (buffer overruns were possible). Change-Id: I42ab8a8018d01f9af43c5ba49f650c3cb5d31dcb Signed-off-by: Jan Matyas <matyas@codasip.com> Reviewed-on: http://openocd.zylin.com/6182 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2021-04-23 08:47:17 +00:00
command_print_sameline(cmd, "\nJTAGSPI flash bank not probed yet\n");
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_OK;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
command_print_sameline(cmd, "flash \'%s\', device id = 0x%06" PRIx32
", flash size = %" PRIu32 " %sbytes\n(page size = %" PRIu32
", read = 0x%02" PRIx8 ", qread = 0x%02" PRIx8
", pprog = 0x%02" PRIx8 ", mass_erase = 0x%02" PRIx8
", sector size = %" PRIu32 " %sbytes, sector_erase = 0x%02" PRIx8 ")",
info->dev.name, info->dev.device_id & 0xFFFFFF,
bank->size / 4096 ? bank->size / 1024 : bank->size,
bank->size / 4096 ? "k" : "", info->dev.pagesize,
info->dev.read_cmd, info->dev.qread_cmd,
info->dev.pprog_cmd, info->dev.chip_erase_cmd,
info->dev.sectorsize / 4096 ?
info->dev.sectorsize / 1024 : info->dev.sectorsize,
info->dev.sectorsize / 4096 ? "k" : "",
info->dev.erase_cmd);
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
return ERROR_OK;
}
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
static const struct command_registration jtagspi_exec_command_handlers[] = {
{
.name = "set",
.handler = jtagspi_handle_set,
.mode = COMMAND_EXEC,
.usage = "bank_id name chip_size page_size read_cmd unused pprg_cmd "
"[ mass_erase_cmd ] [ sector_size sector_erase_cmd ]",
.help = "Set device parameters if not autodetected.",
},
{
.name = "cmd",
.handler = jtagspi_handle_cmd,
.mode = COMMAND_EXEC,
.usage = "bank_id num_resp cmd_byte ...",
.help = "Send low-level command cmd_byte and following bytes, read num_bytes.",
},
{
.name = "always_4byte",
.handler = jtagspi_handle_always_4byte,
.mode = COMMAND_EXEC,
.usage = "bank_id [ on | off ]",
.help = "Use always 4-byte address except for basic 0x03.",
},
COMMAND_REGISTRATION_DONE
};
static const struct command_registration jtagspi_command_handlers[] = {
{
.name = "jtagspi",
.mode = COMMAND_ANY,
.help = "jtagspi command group",
.usage = "",
.chain = jtagspi_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
Constify struct flash_driver instances Instances of struct flash_driver are never written to at runtime. For a small amount of memory saving and also robustness (fewer things for stray pointer writes to hit), mark them const. Change-Id: Iadbbbc2fac0976d892699200000c5f02856729f3 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4803 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-12-13 19:53:59 +00:00
const struct flash_driver jtagspi_flash = {
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
.name = "jtagspi",
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
.commands = jtagspi_command_handlers,
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
.flash_bank_command = jtagspi_flash_bank_command,
.erase = jtagspi_erase,
.protect = jtagspi_protect,
.write = jtagspi_write,
.read = jtagspi_read,
.probe = jtagspi_probe,
Update jtagspi driver for 1-, 2- and 4-byte addresses jtagspi driver always used 3-byte addresses regardless of actual device capcity. Now select 1- to 4-byte addresses depending on device capacity. Some devices need a special command to activate the 4-byte address mode, a special command to accomplish this, and a further command for setting device properties are added. Additionally, restriction (start of range had to be page aligned) removed. Tested with XCS6SLX16 board and W25Q256FV in 3- and 4-byte address modes. Change-Id: I88b2877517a18dac460253ae6d97f3dded054e6c Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/4876 Reviewed-by: Jan Matyas <matyas@codasip.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: zapb <dev@zapb.de> Tested-by: jenkins
2019-01-28 09:37:53 +00:00
.auto_probe = jtagspi_auto_probe,
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
.erase_check = default_flash_blank_check,
flash/nor: implement flash bank deallocation in drivers with simple alloc All drivers which simply allocate one driver_priv memory block per each bank now use default_flash_free_driver_priv() Change-Id: I425bf4213c3632f02dbe11ab819c31eda9b2db62 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4417 Tested-by: jenkins Reviewed-by: Liviu Dudau <liviu@dudau.co.uk> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-15 09:25:50 +00:00
.info = jtagspi_info,
.free_driver_priv = default_flash_free_driver_priv,
flash/nor/jtagspi: add JTAGSPI driver Many FPGA board speak JTAG and have a SPI flash for their bitstream attached to them. The SPI flash is programmed by first uploading a proxy bitstream to the FPGA that connects the JTAG interface to the SPI interface if the IR contains a certain USER instruction. Then the SPI flash can be erase, written, read directly through the JTAG DR. The JTAG and SPI signaling is compatible. Such a proxy bitstream only needs to connect TDO-MISO, TDI-MOSI, TCK-CLK, and the activate the chip select when the IR contains the special instruction and the JTAG state machine is in the DR-SHIFT state. Change-Id: Ibc21d793a83b36fa37e2704966aa5c837c4dd0d2 Signed-off-by: Robert Jordens <jordens@gmail.com> Reviewed-on: http://openocd.zylin.com/2844 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-07-01 09:18:46 +00:00
};
Reference in New Issue Copy Permalink