2022-06-26 23:10:12 +00:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2011-04-14 08:25:01 +00:00
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/***************************************************************************
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* Copyright (C) 2011 by Broadcom Corporation *
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* Evan Hunter - ehunter@broadcom.com *
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***************************************************************************/
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2015-09-21 19:07:46 +00:00
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#ifndef OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H
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#define OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H
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2011-04-14 08:25:01 +00:00
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "rtos.h"
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2021-05-25 07:55:22 +00:00
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extern const struct rtos_register_stacking rtos_standard_cortex_m3_stacking;
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extern const struct rtos_register_stacking rtos_standard_cortex_m4f_stacking;
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extern const struct rtos_register_stacking rtos_standard_cortex_m4f_fpu_stacking;
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extern const struct rtos_register_stacking rtos_standard_cortex_r4_stacking;
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extern const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking;
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2021-09-21 18:43:21 +00:00
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target_addr_t rtos_generic_stack_align8(struct target *target,
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2015-10-05 18:51:10 +00:00
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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2021-09-21 18:43:21 +00:00
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target_addr_t stack_ptr);
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target_addr_t rtos_cortex_m_stack_align(struct target *target,
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rtos: handle STKALIGN adjustments on cortex m
In the case that the STKALIGN bit is set on Cortex M processors, on
entry to an exception - the processor can store an additional 4 bytes
of padding before regular stacking to achieve 8-byte alignment on
exception entry. In the case that this padding is present, the
processor will set bit (1 << 9) in the stacked xPSR register. Use the
new calculate_process_stack callback to take into account the xPSR
register and use it on the standard Cortex_M3 stacking.
Note: Change #2301 had some misinformation regarding the padding. On
Cortex-M the padding is stored BEFORE stacking so xPSR is always
available at a fixed offset.
Tested on a Cortex-M0+ (Atmel SAMR21) board which has STKALIGN fixed
to a '1' such that this alignment always occurs on non-aligned stacks.
Behavior of xPSR verified via the (bad-sorry) assembly program below by
setting a breakpoint on the SVC_Handler symbol. The first time
SVC_Handler is triggered the stack was 0x20000ff8, the second time
SVC_Handler is triggered the stack was 0x20000ffc. Note that in both
cases the interrupt handler gets 0x20000fd8 for a stack pointer.
GDB exerpt:
Breakpoint 1, 0x000040b6 in Reset_Handler ()
(gdb) hbreak SVC_Handler
Hardware assisted breakpoint 2 at 0x40f8
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$3 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40ce 0x21000000
0x20000ff8: 0x0
(gdb) cont
Continuing.
Breakpoint 2, 0x000040f8 in SVC_Handler ()
(gdb) print $msp
$4 = (void *) 0x20000fd8
(gdb) x/9w $msp
0x20000fd8: 0x1 0x2 0x3 0x4
0x20000fe8: 0x88160082 0xa53 0x40e8 0x21000200
0x20000ff8: 0x0
Assembly program:
.cpu cortex-m0plus
.fpu softvfp
.thumb
.syntax unified
.section .vectors
@ pvStack:
.word 0x20001000
@ pfnReset_Handler:
.word Reset_Handler + 1
@ pfnNMI_Handler:
.word 0
@ pfnHardFault_Handler:
.word 0
@ pfnReservedM12:
.word 0
@ pfnReservedM11:
.word 0
@ pfnReservedM10:
.word 0
@ pfnReservedM9:
.word 0
@ pfnReservedM8:
.word 0
@ pfnReservedM7:
.word 0
@ pfnReservedM6:
.word 0
@ pfnSVC_Handler:
.word SVC_Handler + 1
.section .text
.global Reset_Handler
Reset_Handler:
cpsie i
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear
subs r2, r2, #4
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
ldr r0, .stack_start
ldr r2, .stack_last
eors r1, r1
.loop_clear2:
str r1, [r0]
adds r0, r0, #4
cmp r0, r2
bne .loop_clear2
mov sp, r2
movs r0, #1
movs r1, #2
movs r2, #3
movs r3, #4
svc #0
.loop:
b .loop
.align 4
.stack_start:
.word 0x20000f00
.stack_last:
.word 0x20000ffc
@ first call - 0x2000fff8 -- should already be aligned
@ second call - 0x2000fffc -- should hit the alignment code
.global SVC_Handler
SVC_Handler:
bx lr
Change-Id: Id0940e6bbd6a59adee1378c0e86fe86830f0c8fc
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Paul Fertser <fercerpav@gmail.com>
Cc: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Cc: Evan Hunter <evanhunter920@gmail.com>
Cc: Jon Burgess <jburgess777@gmail.com>
Reviewed-on: http://openocd.zylin.com/3003
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-10-05 18:52:43 +00:00
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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2021-09-21 18:43:21 +00:00
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target_addr_t stack_ptr, size_t xpsr_offset);
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2011-04-14 08:25:01 +00:00
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2015-09-21 19:07:46 +00:00
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#endif /* OPENOCD_RTOS_RTOS_STANDARD_STACKINGS_H */
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