2022-06-12 21:48:05 +00:00
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# SPDX-License-Identifier: GPL-2.0-or-later
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Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface
- write speed up to 150 kByte/s on STM32F469I-disco (due to
SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
(tested only in single/quad mode as most devices either don't
support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
(superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
and single 8-line modes, (not in hyper flash mode)
Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.
Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
2016-12-21 09:35:58 +00:00
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# stm32h754i-disco and stm32h750b-dk dual quad qspi.
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# QUADSPI initialization
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# qpi: 4-line mode
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proc qspi_init { qpi } {
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global a
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mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
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mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
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sleep 1 ;# Wait for clock startup
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# PG06: BK1_NCS, PF10: CLK, PF06: BK1_IO3, PF07: BK1_IO2, PF09: BK1_IO1, PD11: BK1_IO0,
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# PG14: BK2_IO3, PG09: BK2_IO2, PH03: BK2_IO1, PH02: BK2_IO0
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# PD11:AF09:V, PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V, PG14:AF09:H
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# PG09:AF09:V, PG06:AF10:H, PH03:AF09:V, PH02:AF09:V
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# Port D: PD11:AF09:V
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mmw 0x58020C00 0x00800000 0x00400000 ;# MODER
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mmw 0x58020C08 0x00C00000 0x00000000 ;# OSPEEDR
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mmw 0x58020C24 0x00009000 0x00006000 ;# AFRH
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# Port F: PF10:AF09:V, PF09:AF10:V, PF07:AF09:V, PF06:AF09:V
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mmw 0x58021400 0x0028A000 0x00145000 ;# MODER
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mmw 0x58021408 0x003CF000 0x00000000 ;# OSPEEDR
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mmw 0x58021420 0x99000000 0x66000000 ;# AFRL
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mmw 0x58021424 0x000009A0 0x00000650 ;# AFRH
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# Port G: PG14:AF09:H, PG09:AF09:V, PG06:AF10:H
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mmw 0x58021800 0x20082000 0x10041000 ;# MODER
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mmw 0x58021808 0x200C2000 0x10001000 ;# OSPEEDR
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mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL
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mmw 0x58021824 0x09000090 0x06000060 ;# AFRH
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# Port H: PH03:AF09:V, PH02:AF09:V
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mmw 0x58021C00 0x000000A0 0x00000050 ;# MODER
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mmw 0x58021C08 0x000000F0 0x00000000 ;# OSPEEDR
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mmw 0x58021C20 0x00009900 0x00006600 ;# AFRL
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# correct FSIZE is 0x1A, however, this causes trouble when
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# reading the last bytes at end of bank in *memory mapped* mode
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# for dual flash mode 2 * mt25ql512
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mww 0x52005000 0x05500058 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=0, FSEL=0, DFM=1, SSHIFT=1, TCEN=1
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mww 0x52005004 0x001A0200 ;# QUADSPI_DCR: FSIZE=0x1A, CSHT=0x02, CKMODE=0
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mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1
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mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1
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# Exit QPI mode
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
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sleep 1
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if { $qpi == 1 } {
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# Write Enable
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
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sleep 1
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# Configure dummy clocks via volatile configuration register
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
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mww 0x52005014 0x01000181 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Volatile Conf. Reg.
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mwh 0x52005020 0xABAB ;# QUADSPI_DR: 0xAB 0xAB for 10 dummy clocks
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sleep 1
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# Write Enable
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x00000106 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enable
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sleep 1
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# Enable QPI mode via enhanced volatile configuration register
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005010 0x00000001 ;# QUADSPI_DLR: 2 data bytes
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mww 0x52005014 0x01000161 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x1, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Write Enhanced Conf. Reg.
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mwh 0x52005020 0x3F3F ;# QUADSPI_DR: 0x3F 0x3F to enable QPI and DPI mode
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sleep 1
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# Enter QPI mode
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x00000135 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=Enter QPI
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sleep 1
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# memory-mapped fast read mode with 4-byte addresses and 10 dummy cycles (for read only)
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x0F283FEC ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0xA, ADSIZE=0x3, ADMODE=0x3, IMODE=0x3, INSTR=Fast READ
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} else {
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# memory-mapped read mode with 4-byte addresses
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x0D003513 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x3, ADMODE=0x1, IMODE=0x1, INSTR=READ
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}
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}
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