2008-07-26 10:32:11 +00:00
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/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifndef MIPS_EJTAG
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#define MIPS_EJTAG
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2009-12-03 12:14:31 +00:00
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#include <jtag/jtag.h>
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2008-07-26 10:32:11 +00:00
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2008-11-12 14:53:19 +00:00
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/* tap instructions */
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2008-07-26 10:32:11 +00:00
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#define EJTAG_INST_IDCODE 0x01
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#define EJTAG_INST_IMPCODE 0x03
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#define EJTAG_INST_ADDRESS 0x08
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#define EJTAG_INST_DATA 0x09
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#define EJTAG_INST_CONTROL 0x0A
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#define EJTAG_INST_ALL 0x0B
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#define EJTAG_INST_EJTAGBOOT 0x0C
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#define EJTAG_INST_NORMALBOOT 0x0D
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#define EJTAG_INST_FASTDATA 0x0E
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#define EJTAG_INST_TCBCONTROLA 0x10
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#define EJTAG_INST_TCBCONTROLB 0x11
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#define EJTAG_INST_TCBDATA 0x12
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2008-10-08 05:09:59 +00:00
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#define EJTAG_INST_BYPASS 0xFF
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2008-07-26 10:32:11 +00:00
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2010-03-08 22:54:18 +00:00
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/* microchip PIC32MX specific instructions */
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#define MTAP_SW_MTAP 0x04
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#define MTAP_SW_ETAP 0x05
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2010-03-16 12:54:08 +00:00
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#define MTAP_COMMAND 0x07
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/* microchip specific cmds */
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#define MCHP_ASERT_RST 0xd1
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#define MCHP_DE_ASSERT_RST 0xd0
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2010-03-18 09:35:45 +00:00
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#define MCHP_ERASE 0xfc
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#define MCHP_STATUS 0x00
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2010-03-08 22:54:18 +00:00
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2010-01-08 22:35:08 +00:00
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/* ejtag control register bits ECR */
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2008-07-26 10:32:11 +00:00
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#define EJTAG_CTRL_TOF (1 << 1)
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#define EJTAG_CTRL_TIF (1 << 2)
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#define EJTAG_CTRL_BRKST (1 << 3)
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#define EJTAG_CTRL_DLOCK (1 << 5)
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#define EJTAG_CTRL_DRWN (1 << 9)
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#define EJTAG_CTRL_DERR (1 << 10)
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#define EJTAG_CTRL_DSTRT (1 << 11)
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#define EJTAG_CTRL_JTAGBRK (1 << 12)
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#define EJTAG_CTRL_SETDEV (1 << 14)
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#define EJTAG_CTRL_PROBEN (1 << 15)
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#define EJTAG_CTRL_PRRST (1 << 16)
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#define EJTAG_CTRL_DMAACC (1 << 17)
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#define EJTAG_CTRL_PRACC (1 << 18)
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#define EJTAG_CTRL_PRNW (1 << 19)
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#define EJTAG_CTRL_PERRST (1 << 20)
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#define EJTAG_CTRL_SYNC (1 << 23)
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#define EJTAG_CTRL_DNM (1 << 28)
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#define EJTAG_CTRL_ROCC (1 << 31)
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/* Debug Register (CP0 Register 23, Select 0) */
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#define EJTAG_DEBUG_DSS (1 << 0)
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#define EJTAG_DEBUG_DBP (1 << 1)
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#define EJTAG_DEBUG_DDBL (1 << 2)
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#define EJTAG_DEBUG_DDBS (1 << 3)
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#define EJTAG_DEBUG_DIB (1 << 4)
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#define EJTAG_DEBUG_DINT (1 << 5)
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#define EJTAG_DEBUG_OFFLINE (1 << 7)
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#define EJTAG_DEBUG_SST (1 << 8)
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#define EJTAG_DEBUG_NOSST (1 << 9)
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#define EJTAG_DEBUG_DDBLIMPR (1 << 18)
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#define EJTAG_DEBUG_DDBSIMPR (1 << 19)
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#define EJTAG_DEBUG_IEXI (1 << 20)
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#define EJTAG_DEBUG_DBUSEP (1 << 21)
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#define EJTAG_DEBUG_CACHEEP (1 << 22)
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#define EJTAG_DEBUG_MCHECKP (1 << 23)
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#define EJTAG_DEBUG_IBUSEP (1 << 24)
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#define EJTAG_DEBUG_COUNTDM (1 << 25)
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#define EJTAG_DEBUG_HALT (1 << 26)
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#define EJTAG_DEBUG_DOZE (1 << 27)
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#define EJTAG_DEBUG_LSNM (1 << 28)
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#define EJTAG_DEBUG_NODCR (1 << 29)
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#define EJTAG_DEBUG_DM (1 << 30)
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#define EJTAG_DEBUG_DBD (1 << 31)
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2008-11-12 14:53:19 +00:00
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/* implementaion register bits */
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2010-01-08 22:35:08 +00:00
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#define EJTAG_IMP_R3K (1 << 28)
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#define EJTAG_IMP_DINT (1 << 24)
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2008-11-12 14:53:19 +00:00
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#define EJTAG_IMP_NODMA (1 << 14)
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#define EJTAG_IMP_MIPS16 (1 << 16)
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2010-01-08 22:35:08 +00:00
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#define EJTAG_DCR_MIPS64 (1 << 0)
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2008-11-12 14:53:19 +00:00
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2010-01-08 22:35:08 +00:00
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/* Debug Control Register DCR */
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2008-11-17 17:56:44 +00:00
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#define EJTAG_DCR 0xFF300000
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2010-01-08 22:35:08 +00:00
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#define EJTAG_DCR_ENM (1 << 29)
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#define EJTAG_DCR_DB (1 << 17)
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#define EJTAG_DCR_IB (1 << 16)
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#define EJTAG_DCR_INTE (1 << 4)
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/* breakpoint support */
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2008-11-17 17:56:44 +00:00
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#define EJTAG_IBS 0xFF301000
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#define EJTAG_IBA1 0xFF301100
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#define EJTAG_DBS 0xFF302000
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#define EJTAG_DBA1 0xFF302100
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2010-01-07 20:56:07 +00:00
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#define EJTAG_DBCn_NOSB (1 << 13)
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#define EJTAG_DBCn_NOLB (1 << 12)
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#define EJTAG_DBCn_BLM_MASK 0xff
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#define EJTAG_DBCn_BLM_SHIFT 4
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#define EJTAG_DBCn_BE (1 << 0)
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2008-11-17 17:56:44 +00:00
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2012-02-05 12:03:04 +00:00
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struct mips_ejtag {
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2009-11-13 11:19:35 +00:00
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struct jtag_tap *tap;
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2009-06-18 07:09:35 +00:00
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uint32_t impcode;
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uint32_t idcode;
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uint32_t ejtag_ctrl;
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2011-01-04 12:29:49 +00:00
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int fast_access_save;
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2013-02-24 16:05:28 +00:00
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uint32_t reg8;
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uint32_t reg9;
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mips: m4k alternate pracc code. Patch 1
This patch and the following patches define another way of doing processor access without the need to read back
the pracc address as needed in current pracc code.
Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
Most of the processor accesses are fetch and some are store accesses.
After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
The pracc address for a store depends only on the store instruction given before.
m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
For reference: MD00249 mips32 m4k manual.
A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
current code or by the new one to generate the sequence of pracc accesses.
For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
The pracc bit is not checked before execution, is checked after the queue has been executed.
Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
between scans is added by calling jtag_add_cloks().
A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
current code is executed, if lower, new code is executed.
Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1193
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-03-03 09:50:42 +00:00
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unsigned scan_delay;
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int mode;
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2009-11-13 16:43:36 +00:00
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};
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2008-07-26 10:32:11 +00:00
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2011-03-31 21:31:37 +00:00
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void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
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2010-03-17 17:24:22 +00:00
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int new_instr);
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2009-11-13 16:43:36 +00:00
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int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
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int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
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int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
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mips: m4k alternate pracc code. Patch 1
This patch and the following patches define another way of doing processor access without the need to read back
the pracc address as needed in current pracc code.
Current pracc code is executed linearly and unconditionally. The processor starts execution at 0xff200200
and the fetch address is ever incremented by 4, including the last instruction in the delay slot of the branch to start.
Most of the processor accesses are fetch and some are store accesses.
After a previous patch regarding the way of restoring registers (reg8 and reg9), there are no load processor accesses.
The pracc address for a store depends only on the store instruction given before.
m4k core has a 5 stage pipeline and the memory access is done in the 3rth stage. This means that the store access
will not arrive immediately after a store instruction, it appears after another instruction enters the pipeline.
For reference: MD00249 mips32 m4k manual.
A new struct pracc_queue_info is defined to help each function in generating the code. The field pracc_list holds in the
lower half the list of instructions and in the upper half the store addressess, if any. In this way the list can be used by
current code or by the new one to generate the sequence of pracc accesses.
For every pracc access only one scan to register "all" is used by calling the new function mips_ejtag_add_scan_96().
This function does not call jtag_execute_queue(), all the scans needed can be queued before calling for execution.
The pracc bit is not checked before execution, is checked after the queue has been executed.
Without calling the wait function the code works much faster, but the scan frequency must be limited. For pic32mx
with core clock at 4Mhz works up to 600Khz and with 8Mhz up to 1200. To increase the scan frequency a delay
between scans is added by calling jtag_add_cloks().
A time delay in nano seconds is stored in scan_delay, a new field in ejtag_info, and a handler is provided for it.
A mode field is added to ejtag_info to hold the working mode. If a time delay of 2ms (2000000 ns) or higher is set,
current code is executed, if lower, new code is executed.
Initial default values are set in function mips32_init_arch_info. A reset does not change this settings.
Change-Id: I266bdb386b24744435b6e29d8489a68c0c15ff65
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/1193
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-03-03 09:50:42 +00:00
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void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
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uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
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2011-04-04 13:33:04 +00:00
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void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
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2009-11-13 16:43:36 +00:00
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int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
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2011-03-31 22:00:39 +00:00
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void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
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2010-03-16 12:54:08 +00:00
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int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
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2010-12-29 20:15:48 +00:00
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int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
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2008-07-26 10:32:11 +00:00
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2009-11-13 16:43:36 +00:00
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int mips_ejtag_init(struct mips_ejtag *ejtag_info);
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int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
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2008-07-26 10:32:11 +00:00
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2012-02-05 12:03:04 +00:00
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static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
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2011-05-31 07:33:01 +00:00
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{
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uint8_t *in = (uint8_t *)arg;
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*((uint32_t *)arg) = le_to_h_u32(in);
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}
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2008-07-26 10:32:11 +00:00
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#endif /* MIPS_EJTAG */
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